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Title: US6311313: X-Y grid tree clock distribution network with tunable tree and grid networks
[ Derwent Title ]

Country: US United States of America

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22 pages

Inventor: Camporese, Peter J.; Hopewell Junction, NY
Deutsch, Alina; Chappaqua, NY
McNamara, Timothy Gerard; Fishkill, NY
Restle, Phillip John; Katonah, NY
Webber, David Allan; Poughkeepsie, NY

Assignee: International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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Published / Filed: 2001-10-30 / 1998-12-29

Application Number: US1998000222141

IPC Code: Advanced: G06F 1/10;
Core: more...
IPC-7: G06F 9/45;

ECLA Code: G06F1/10;

U.S. Class: Current: 716/113;
Original: 716/006; 716/021; 716/008; 716/009;

Field of Search: 716/006

Priority Number:
1998-12-29  US1998000222141

Abstract:     An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid. Electrical simulation models are created for network components and clustered grid loads are substituted with smoothed clustered grid loads. A set of NSECTOR electrical net lists are next created by extracting a net list with associated X-Y grid wires cut to isolate each sector net list from its neighboring sectors. Each NSECTOR electrical net list is then tuned, wherein the smoothed clustered grid loads represent an approximation of the effects of the neighboring sectors of each NSECTOR electrical net list.

Attorney, Agent or Firm: Tassinari, Robert P. ;

Primary / Asst. Examiners: Smith, Matthew; Thompson, A. M.

Maintenance Status: E2 Expired  Check current status

INPADOC Legal Status: Show legal status actions

Parent Case:

    The present invention is related to co-pending patent application Ser. No. 09/222,143, entitled "X-Y Grid Tree Tuning Method," by Restle et al., filed of even date herewith. This co-pending application and the present invention are commonly assigned to the International Business Machines Corporation, Armonk, N.Y. This co-pending application is hereby incorporated by reference in its entirety into the present application.

Family: None

First Claim:
Show all 28 claims
What is claimed is:     1. A clock distribution network, comprising:
  • one or more primary inputs for accepting one or more primary clock signals;
  • a tree coupled to the one or more primary inputs, the tree deriving separate clock signals from the one or more primary clock signals and including N levels of sub-trees where N is greater than 1, wherein the separate clock signals are produced at tree end points and wherein a number of said tree end points for level N is greater than the number of clock signals for level N-1;
  • one or more repower drivers buffering the separate clock signals between any two levels of trees;
  • an X-Y grid vertically and horizontally connecting all the tree end points; wherein no drivers are used at connection points of the tree end points to the X-Y grid; and
  • local distribution wiring, coupled to the X-Y grid, distributing a clock signal on the X-Y grid to one or more clock pin locations.

Background / Summary: Show background / summary

Drawing Descriptions: Show drawing descriptions

Description: Show description

Forward References: Show 98 U.S. patent(s) that reference this one

U.S. References: Go to Result Set: All U.S. references   |  Forward references (98)   |   Backward references (13)   |   Citation Link

Patent  Pub.Date  Inventor Assignee   Title
Get PDF - 8pp US5109168  1992-04 Rusu  Sun Microsystems, Inc. Method and apparatus for the design and optimization of a balanced tree for clock distribution in computer integrated circuits
Get PDF - 28pp US5163068  1992-11 El-Amawy   Arbitrarily large clock networks with constant skew bound
Get PDF - 19pp US5430397  1995-07 Itoh et al.  Hitachi, Ltd. Intra-LSI clock distribution circuit
Get PDF - 16pp US5537498  1996-07 Bausman et al.  Cray Research, Inc. Optical clock distribution system
Get PDF - 26pp US5557779  1996-09 Minami  Kabushiki Kaisha Toshiba Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew
Get PDF - 25pp US5638291  1997-06 Li et al.  VLSI Technology, Inc. Method and apparatus for making integrated circuits by inserting buffers into a netlist to control clock skew
Get PDF - 8pp US5656963  1997-08 Masleid et al.  International Business Machines Corporation Clock distribution network for reducing clock skew
Get PDF - 10pp US5668484  1997-09 Nomura  NEC Corporation High frequency clock signal distribution circuit with reduced clock skew
Get PDF - 13pp US5668490  1997-09 Mitra et al.  Sun Microsystems, Inc. Flip-flop with full scan capability
Get PDF - 12pp US5880607  1999-03 Mitra  Sun Microsystems, Inc. Clock distribution network with modular buffers
Get PDF - 17pp US6006025  1999-12 Cook et al.  International Business Machines Corporation Method of clock routing for semiconductor chips
Get PDF - 11pp US6088254  2000-07 Kernami  Lucent Technologies Inc. Uniform mesh clock distribution system
Get PDF - 9pp US6157237  2000-12 Mitra  Sun Microsystems, Inc. Reduced skew control block clock distribution network
Foreign References: None

Other References:
  • N. Menezes et al., Skew Reduction in Clock Trees Using Wire Width Optimization, 1993 Custom Integrated Circuits Conference, pp. 9.6.1-9.6.4, May 1993.*
  • K. Yip, Clock Tree Distribution, IEEE Potentials, pp. 11-14, Apr. 1997.*
  • M. Nekili et al., Pipelined H-Trees for High-Speed Clocking of Large Integrated Systems in Presence of Process Variations, IEEE Transactions on VLSI Systems, pp. 161-174, Jun. 1997.* (14 pages) [ISI abstract]
  • C. L. Ratzlaff et al., "RICE: Rapid Interconnect Circuit Evaluation Using AWE," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, No. 6, Jun. 1994, pp. 763-776. (14 pages) Cited by 10 patents [ISI abstract]
  • P. J. Restle et al., "Measurement and Modeling of On-Chip Transmission Line Effects in a 400 MHz Microprocessor," IEEE Journal of Solid-State Circuits, vol. 33, No. 4, Apr. 1998, pp. 662-665. (4 pages) Cited by 4 patents [ISI abstract]

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