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 Title: |
US6320438:
Duty-cycle correction driver with dual-filter feedback loop
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Arcus, Christopher G.; San Jose, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2001-11-20
/ 2000-08-17
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| Application Number: |
US2000000641282
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| IPC Code: |
Advanced:
H03K 5/156;
Core:
more...
IPC-7:
H03K 3/017;
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| ECLA Code: |
H03K5/156D;
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| U.S. Class: |
Current:
327/175;
327/037;
327/165;
327/285;
Original:
327/175;
327/037;
327/165;
327/285;
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| Field of Search: |
327/037,172,173,174,175,170,277,278,261,263,264,266,284,285,287,268,165,166,113,114
375/238,241
331/040,177 R
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| Priority Number: |
| 2000-08-17 |
US2000000641282 |
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| Abstract: |
A clock generator has a duty cycle correction circuit that adjusts the duty cycle to 50%. A modulator is an inverter with extra source-limiting transistors in series to the power and ground supplies. A control voltage of about Vcc/2 is applied to the source-limiting transistors, causing them to operate in the linear region with limited current. A slow-slew output from the modulator is buffered by a driver. The driver output is filtered by a linear detector with a series resistor and input capacitor. The detector output is compared to a reference voltage of Vcc/2 by an error amp. The error amp generates the control voltage fed back to the modulator. An output capacitor creates a dominant pole with the error amp to ensure stability. A variable-threshold gate can be added between the driver output and the detector to separately adjust the measurement threshold voltage from the reference voltage to the error amp.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Callahan, Timothy P.; Nguyen, Minh
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 15 claims |
I claim:
1. A duty-cycle-correcting clock driver comprising:
- clock input for receiving an input clock with an input duty cycle that varies from a target duty cycle;
- a modulator, receiving the input clock and generating an intermediate clock, for adjusting rise and fall delays of the intermediate clock in response to a control signal to adjust the input duty cycle;
- a driver, receiving the intermediate clock, for generating a final clock, the final clock being corrected to the target duty cycle by the modulator;
- a feedback loop for generating the control signal to the modulator, receiving the final clock, the feedback loop including:
- an error amplifier for amplifying a difference between a first input and a reference voltage applied to a second input to generate an amp output;
- a detector filter having a series resistor between the final clock and the first input of the error amplifier, the detector filter also having an input capacitor attached to the first input; and
- an output capacitor, coupled to the amp output, for filtering the amp output to generate the control signal to the modulator,
- wherein the modulator comprises:
- a source-limiting p-channel transistor having a gate coupled to the control signal and a source connected to a power supply, for limiting charging current in response to the control signal;
- a switching p-channel transistor, coupled to receive charging current from the source-limiting p-channel transistor, having a gate coupled to the input clock and a drain driving the intermediate clock;
- a source-limiting n-channel transistor having a gate coupled to the control signal and a source connected to a ground supply, for limiting discharging current in response to the control signal;
- a switching n-channel transistor, coupled to sink discharging current to the source-limiting n-channel transistor, having a gate coupled to the input clock and a drain driving the intermediate clock,
- whereby the feedback loop includes the series resistor and senses the final clock to generate the control signal for the modulator.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 25 U.S. patent(s) that reference this one
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