Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank (US6330636)

wherein the data input and output buffer is synchronously operated for clocking data on the data inputs on a rising edge and a falling edge of a data strobe signal on the bi-directional data strobe inputs.

Background / Summary:

Show background / summary

Drawing Descriptions:

Show drawing descriptions

Description:

Show description

Forward References:

Show 25 U.S. patent(s) that reference this one

U.S. References:

Go to Result Set: All U.S. references | Forward references (25) | Backward references (46) | Citation Link

Patent	Pub.Date	Inventor	Assignee	Title
US4577293	1986-03	Matick et al.	International Business Machines Corporation	Distributed, on-chip cache
US4608666	1986-08	Uchida	Tokyo Shibaura Denki Kabushiki Kaisha	Semiconductor memory
US4725945	1988-02	Kronstadt et al.	International Business Machines Corp.	Distributed cache in dynamic rams
US4794559	1988-12	Greeberger	American Telephone and Telegraph Company, AT&T Bell Laboratories	Content addressable semiconductor memory arrays
US4870622	1989-09	Aria et al.	Advanced Micro Devices, Inc.	DRAM controller cache
US4894770	1990-01	Ward et al.	Massachusetts Institute of Technology	Set associative memory
US4926385	1990-05	Fujishima et al.	Mitsubishi Denki Kabushiki Kaisha	Semiconductor memory device with cache memory addressable by block within each column
US4943944	1990-07	Sakui et al.	Kabushiki Kaisha Toshiba	Semiconductor memory using dynamic ram cells
US5025421	1991-06	Cho		Single port dual RAM
US5111386	1992-05	Fujishima et al.	Mitsubishi Denki Kabushiki Kaisha	Cache contained type semiconductor memory device and operating method therefor
US5134616	1992-07	Barth, Jr. et al.	International Business Machines Corporation	Dynamic RAM with on-chip ECC and optimized bit and word redundancy
US5148396	1992-09	Nakada et al.	NEC Corporation	Semiconductor integrated circuit memory enabling memory write masking
US5179687	1993-01	Hidaka et al.	Mitsubishi Denki Kabushiki Kaisha	Semiconductor memory device containing a cache and an operation method thereof
US5184320	1993-02	Dye	Texas Instruments Incorporated	Cached random access memory device and system
US5184325	1993-02	Lipovski	Board of Regents, The University of Texas System	Dynamic associative memory with logic-in-refresh
US5214610	1993-05	Houston	Texas Instruments Incorporated	Memory with selective address transition detection for cache operation
US5226009	1993-07	Arimoto	Mitsubishi Denki Kabushiki Kaisha	Semiconductor memory device supporting cache and method of driving the same
US5226139	1993-07	Fujishima et al.	Mitsubishi Denki Kabushiki Kaisha	Semiconductor memory device with a built-in cache memory and operating method thereof
US5226147	1993-07	Fujishima et al.	Mitsubishi Denki Kabushiki Kaisha	Semiconductor memory device for simple cache system
US5249282	1993-09	Segers	Benchmarq Microelectronics, Inc.	Integrated cache memory system with primary and secondary cache memories
US5305280	1994-04	Hayano	Mitsubishi Denki Kabushiki Kaisha	Semiconductor memory device having on the same chip a plurality of memory circuits among which data transfer is performed to each other and an operating method thereof
US5329489	1994-07	Diefendorff	Texas Instruments Incorporated	DRAM having exclusively enabled column buffer blocks
US5353427	1994-10	Fujishima et al.	Mitsubishi Denki Kabushiki Kaisha	Semiconductor memory device for simple cache system with selective coupling of bit line pairs
US5359722	1994-10	Chan et al.	International Business Machines Corporation	Method for shortening memory fetch time relative to memory store time and controlling recovery in a DRAM
US5381370	1995-01	Lacey et al.	Cypress Semiconductor Corporation	Memory with minimized redundancy access delay
US5390308	1995-02	Ware et al.	Rambus, Inc.	Method and apparatus for address mapping of dynamic random access memory
US5404338	1995-04	Murai et al.	Mitsubishi Denki Kabushiki Kaisha	Synchronous type semiconductor memory device operating in synchronization with an external clock signal
US5421000	1995-05	Fortino et al.	International Business Machines Corp.	Memory subsystem having a static row memory and a dynamic RAM
US5471601	1995-11	Gonzales	Intel Corporation	Memory device and method for avoiding live lock of a DRAM with cache
US5539696	1996-07	Patel		Method and apparatus for writing data in a synchronous memory having column independent sections and a method and apparatus for performing write mask operations
US5568427	1996-10	Takamae	Fujitsu Limited	Memory and method of reading out of the memory
US5600605	1997-02	Schaefer	Micron Technology, Inc.	Auto-activate on synchronous dynamic random access memory
US5627791	1997-05	Wright et al.	Micron Technology, Inc.	Multiple bank memory with auto refresh to specified bank
US5636173	1997-06	Schaefer	Micron Technology, Inc.	Auto-precharge during bank selection
US5655105	1997-08	McLaury	Micron Technology, Inc.	Method and apparatus for multiple latency synchronous pipelined dynamic random access memory
US5666321	1997-09	Schaefer	Micron Technology, Inc.	Synchronous DRAM memory with asynchronous column decode
US5673233	1997-09	Wright et al.	Micron Technology, Inc.	Synchronous memory allowing early read command in write to read transitions
US5787457	1998-07	Miller et al.	International Business Machines Corporation	Cached synchronous DRAM architecture allowing concurrent DRAM operations
US5875134	1999-02	Cloud	Micron Technology, Inc.	Data communication for memory
US5986948	1999-11	Cloud	Micron Technology, Inc.	Data communication for memory
US6044026	2000-03	Morgan	Micron Technology, Inc.	Trap and delay pulse generator for a high speed clock
US6044032	2000-03	Li	Micron Technology, Inc.	Addressing scheme for a double data rate SDRAM
US6067260	2000-05	Ooishi et al.	Mitsubishi Denki Kabushiki Kaisha	Synchronous semiconductor memory device having redundant circuit of high repair efficiency and allowing high speed access
US6081477	2000-06	Li	Micron Technology, Inc.	Write scheme for a double data rate SDRAM
US6104650	2000-08	Shore	Micron Technology, Inc.	Sacrifice read test mode
US6111807	2000-08	Ooishi	Mitsubishi Denki Kabushiki Kaisha	Synchronous semiconductor memory device allowing easy and fast text

Foreign References:

Publication	Date	IPC Code	Assignee	Title
DE4118847A1	1991-12	G11C 7/00	Kabushiki Kaisha Toshiba, Kawasaki, Kanagawa, JP	Halbleiterspeicheranordnung mit ferroelektrischem Kondensator
JP60258792	1985-12
JP63081692	1988-04
JP01159891	1989-06

Other References:

"DM 2202 EDRAM 1Mb×4 Enchanced Dynamic RAM--Product Review," May 22, 1991, Ramtron, Colorado Springs, Colorado.

Sartore, "New Generation of Fast Enhanced DRAMS Replace Static RAM Caches in High-end PC Work Station" 1991.

Niijima et al, "QRAM--Quick Access Memory System", IEEE International Conference, pp. 417-420, Sep. 17, 1990.

Bursky, "Combination DRAM-SRAM Removes Secondary Caches", Electr. Design, vol. 40, No. 2, pp. 39-43, Jan. 23, 1992. Cited by 11 patents [ISI abstract]

Goodman et al. "Use of Static Column RAM as a Memory Hierarchy," 11^th Annual Symposium, IEEE, 1984, pp. 167-174.

Ohta et al., "A 1 MB DRAM with 33 MHz Serial I/O Ports" Digest of Technical Papers, 1986 IEEE, pp. 274-275 (1986).

Dosaka et al., "A 100MHz 4Mb Cache DRAM with Fast Copy-back Scheme," Digest of Technical Papers, 1992 IEEE International Solid-State Circuits Conference, p. 148-149 (6/92).

Nominate this for the Gallery...


		Copyright © 1997-2010 Thomson Reuters
		Subscriptions \| Web Seminars \| Privacy \| Terms & Conditions \| Site Map \| Contact Us \| Help