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Title: US6342823: System and method for reducing calculation complexity of lossy, frequency-dependent transmission-line computation
[ Derwent Title ]


Country: US United States of America

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17 pages

 
Inventor: Dansky, Allan Harvey; Poughkeepsie, NY
Deutsch, Alina; Chappaqua, NY
Kopcsay, Gerard Vincent; Yorktown Heights, NY
Restle, Phillip John; Katonah, NY
Smith, Howard Harold; Beacon, NY

Assignee: International Business Machines Corp., Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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Published / Filed: 2002-01-29 / 1998-08-26

Application Number: US1998000140643

IPC Code: Advanced: G06F 17/50;
Core: more...
IPC-7: H01P 1/00; H01P 5/00;

ECLA Code: G06F17/50C4;

U.S. Class: Current: 333/001; 333/099.R;
Original: 333/001; 333/099.R;

Field of Search: 333/001,263,99 R

Priority Number:
1998-08-26  US1998000140643

Abstract: A method and system for reducing the computation complexity and improving accuracy of delay and crosstalk calculation in transmission-lines with frequency-dependent losses. An analysis tool based on restricted coupled-line topologies, simple two-dimensional to three-dimensional RLC matrix conversion, and use of prestored synthesized circuits that accurately capture frequency-dependent loss effects. The CAD tool can handle frequency-dependent resistive and inductive effects for coupled-interconnections on large microprocessor chips with >10K of critical nets. This is done in an interactive manner during the design cycle and allows first path fast product design.

Attorney, Agent or Firm: Scully, Scott, Murphy & Presser ; Morris, Daniel P. ;

Primary / Asst. Examiners: Pascal, Robert; Glenn, Kimberly E

Maintenance Status: E2 Expired  Check current status

INPADOC Legal Status: Show legal status actions

Family: None

First Claim:
Show all 6 claims
Having thus described our invention, what we claim as new and desire to secure with the letters patent is:     1. A method for reducing the computation complexity and improving the accuracy of delay and crosstalk calculations for transmission-lines of on-chip interconnections with frequency-dependent losses, comprising the steps of:
  • providing a wiring plan for an integrated circuit having interconnected circuits and transmission lines;
  • identifying a group of constituent parts of the integrated circuit, each of said parts having a restricted topology;
  • defining a unique distributed network for each of said parts, each of said networks including dc resistance and high-frequency inductance values;
  • associating an R(f) matrix and an L(f) matrix with each of the distributed networks, where the R(f) matrix is a matrix of frequency dependent resistance values, and the L(f) matrix is a matrix of frequency dependent inductance values;
  • estimating delay and crosstalk of the interconnection on the basis of said associated R(f) and L(f) matrices;
  • allowing a range of line dimensions within each of said constituent parts; and
  • defining each distributed network in terms of unique two-dimensional to three-dimensional scaling constants.


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Forward References: Show 14 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (14)   |   Backward references (0)   |   Citation Link

       
Foreign References: None

Other References:
  • Rubin, B.J. et al. (1993) "Calculation of Multi-Port Paramters of Electronic Packages Using a General Purpose Electromagnetic Code", Proceedings of the 2nd IEEE Topical Meeting on Electrical Performance of Electronic Packaging, EPEP'93, pp. 37-39.
  • Smith, H.H., "Multi-Reflection Algorithm for Timed Statistical Coupled Noise Checking", Proceedings of 4th IEEE Topical Meeting on Electrical Performance of Electronic Packaging, pp. 4-6.
  • Dansky, A.H., et al. (1996) "Analysis and Results of Net Coupling Within a High Performance of Electronic Packaging", pp. 36-38.
  • Tripathi, V.K. et al. (1988) "Equivalent Circuit Modeling of Losses and Dispersion in Single and Coupled Lines for Microwave and Millimeter--Wave Integrated Cicuits", IEEE Transactions on Microwave Theory and Techniques.
  • Kim, S. et al. (1997) "Time Domain Multiconductor Transmission Line Analysis Using Effective Internal Impedance", Proceedings of the 6th IEEE Topical Meeting on Electrical Performance of Electronic Packaging, pp. 255-258.
  • Krauter, B. et al. "Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis", submitted to DAC'98.
  • Deutsch, A. et al. (1995) "Modeling and Characterization of Long On-Chip Interconnections for High-Performance Microprocessors", IBM Journal Res. Develop., vol. 39-547-567. (21 pages) Cited by 6 patents [ISI abstract]
  • Ling, D.D. et al. (1987) "Interconnection Modeling" in Advances in CAD for VLSI, 3, Part II, Circuit Analysis, Simulation and Design, pp. 211-291.
  • Shepard, K.L., (1997), Design Methodology for the S/390 Parallel Enterprise Server G4 Microprocessors, IBM Journal Res. Develop., vol. 41:515-547. (33 pages) Cited by 8 patents [ISI abstract]
  • Deutsch, A., et al. (1997) "The Importance of Inductance and Inductive Coupling for On-Chip Wiring", Proceedings of 6th IEEE Topical Meeting on Electrical Performance of Electronic Packaging, pp. 53-56.
  • Sigal, L. et al. (1997) "Circuit Design Techniques for the High-Performance CMOS IBM S/390 Parallel Enterprise Server G4 Microprocessor", IBM Journal Res. Develop, vol. 4:489-503. (15 pages) Cited by 10 patents [ISI abstract]
  • Giedke, B.A. et al. (1997) "A 600 MHz Superscaler RISC Microprocessor with Out-of-Order Execution", IEEE International Solid State Circuits Conference, pp. 656-657.
  • Silberman, J. et al. (1998) "A 1.0 GHz Single-Issue 64b PowerPC Integer Processor", IEEE International Solid State Circuits Conference.
  • Deutsch, A. et al. (1997) "When Are Transmission-Line Effects Important for On-Chip Interconnections", IEEE International Solid State Circuits Conference, vol. 45:1836-1846. (11 pages) Cited by 6 patents [ISI abstract]


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