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 Title: |
US6349361:
Methods and apparatus for reordering and renaming memory references in a multiprocessor computer system
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Altman, Erik; Danbury, CT
Ebcioglu, Kemal; Katonah, NY
Gschwind, Michael; Danbury, CT
Sathaye, Sumedh; Fishkill, NY
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| Assignee: |
International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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| Published / Filed: |
2002-02-19
/ 2000-03-31
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| Application Number: |
US2000000541271
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| IPC Code: |
Advanced:
G06F 9/38;
G06F 12/08;
Core:
more...
IPC-7:
G06F 12/00;
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| ECLA Code: |
G06F9/38D4; G06F9/38E2; G06F9/38H2; G06F12/08B4P;
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| U.S. Class: |
Current:
711/121;
711/124;
711/145;
711/146;
711/E12.026;
712/E09.048;
712/E09.05;
712/E09.061;
Original:
711/121;
711/124;
711/145;
711/146;
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| Field of Search: |
711/121,124,145,146
712/216,217,218,219,235
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| Priority Number: |
| 2000-03-31 |
US2000000541271 |
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| Abstract: |
There is provided a method for reordering and renaming memory references in a multiprocessor computer system having at least a first and a second processor. The first processor has a first private cache and a first buffer, and the second processor has a second private cache and a second buffer. The method includes the steps of, for each of a plurality of gated store requests received by the first processor to store a datum, exclusively acquiring a cache line that contains the datum by the first private cache, and storing the datum in the first buffer. Upon the first buffer receiving a load request from the first processor to load a particular datum, the particular datum is provided to the first processor from among the data stored in the first buffer based on an in-order sequence of load and store operations. Upon the first cache receiving a load request from the second cache for a given datum, an error condition is indicated and a current state of at least one of the processors is reset to an earlier state when the load request for the given datum corresponds to the data stored in the first buffer.
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| Attorney, Agent or Firm: |
F. Chau & Associates, LLP ;
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| Primary / Asst. Examiners: |
Kim, Matthew; Elmore, Stephen
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| Maintenance Status: |
E1 Expired Check current status
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| INPADOC Legal Status: |
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| Family: |
None
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First Claim:
Show all 25 claims |
What is claimed is:
1. A method for reordering and renaming memory references in a multiprocessor computer system having at least a first and a second processor, the first processor having a first private cache and a first buffer, the second processor having a second private cache and a second buffer, said method comprising the steps of:
- for each of a plurality of gated store requests received by the first processor to store a datum,
- exclusively acquiring a cache line that contains the datum by the first private cache, and
- storing the datum in the first buffer;
- upon the first buffer receiving a load request from the first processor to load a particular datum,
- providing the particular datum to the first processor from among the data stored in the first buffer based on an in-order sequence of load and store operations; and
- upon the first cache receiving a load request from the second cache for a given datum,
- indicating an error condition and resetting a current state of at least one of the processors to an earlier state when the load request for the given datum corresponds to the data stored in the first buffer.
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| Background / Summary: |
Show background / summary
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 5 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other References: |
Gschwind et al., "Binary Translation and Architecture Convergence Issues for IBM System/390", ACM Press, Intl Conference on Supercomputing, pp 336-347, 2000.*
Lenoski et al., "The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor", IEEE Computer Architecture, pp 149-159, May 1990.*
Sinharoy et al., "Improving Software MP Efficiency for Shared Memory Systems", IEEE System Sciences, vol. 1, pp 111-120, Jan. 1996.*
Austin, et al., "Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency", IEEE Proceedings of MICRO-28, Nov. 1995, pp. 82-92.
Lamport, "How to Make a Multiprocessor Computer Than Correctly Executes Multiprocess Programs", IEEE Transaction on Computers, vol. C-28, No. 9, Sep. 1979.
Adve, et al., "Shared Memory Consistency Models: A Tutorial", Tech. Rpt. 9512, Dept. Of Elect. And Computer Eng., Rice University, pp. 1-23, Sep. 1995.
Postiff, et al., "The Limits of Instruction Level Parallelism in SPEC95 Appliations", Int. Conf. On Architectural Support for Programming Languages and Operating Systems (ASPLOS--VIII), Workshop on Interaction Between Compilers and Computer Architecture, Oct. 1998.
Franklin, et al., "ARB: A Hardware Mechanism for Dynamic Reordering of Memory References", IEEE Transactions on Computers, vol. 45, No. 5, May 1996, pp. 552-571.
(20 pages)
Cited by 20 patents
[ISI abstract]
Moshovos, et al., "Streamlining Inter-operation Memory Communication via Data Dependence Prediction", IEEE Proc. Of 30th Annual Symposium on Microarchitecture Research, Triangle Park, N. Carolina, pp. 235-245, Dec. 1997.
Tyson, et al., "Improving the Accuracy and Performance of Memory Communication Through Renaming", 1997 IEEE Proc. Of 30th Annual Symposium on Microarchitecture Research, Triangle Park, N. Carolina, pp. 218-227, Dec. 1997.
Mahlke, et al., "Sentinel Scheduling for VLIW and Superscaler Process", Int. Conf. On Architectural Support for Programming Languages and Operating Systems, (ASPLOS V), MA, USA, pp. 238-247, Oct. 1992.
UNIX Systems for Modern Architectures, Addison Wesley, pp. 285-349, Sep. 1994.
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