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 Title: |
US6351138:
Zero-DC-power active termination with CMOS overshoot and undershoot clamps
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Wong, Anthony Yap; Cupertino, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2002-02-26
/ 2001-03-22
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| Application Number: |
US2001000681344
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| IPC Code: |
Advanced:
H03K 17/16;
Core:
more...
IPC-7:
H03K 17/16;
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| ECLA Code: |
H04L25/02K11;
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| U.S. Class: |
Current:
326/030;
326/086;
Original:
326/030;
326/086;
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| Field of Search: |
326/030,83,86,89,90
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| Priority Number: |
| 2001-03-22 |
US2001000681344 |
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| Abstract: |
An active terminating circuit has n-channel and p-channel sensing transistors with gates connected to a transmission line. The sensing transistors drive a back node connected to a pair of capacitors. One capacitor drives a p-gate node coupled to a gate of a p-channel clamping transistor, while the other capacitor drives an n-gate node coupled to a gate of an n-channel clamping transistor. The drains of the clamping transistors are connected to the transmission line. Resistors pull the p-gate node to the power-supply voltage and pull the n-gate node to ground when no transitions occur on the transmission line to achieve zero standby power. When a transition is detected, it is inverted and coupled through the capacitors to the p-gate and n-gate nodes. The p-channel clamping transistor is turned on for rising transitions, while the n-channel clamping transistor is turned on for falling transitions. Limiting transistors limit gate-node swings.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Tokar, Michael; Le, Don Phu
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| INPADOC Legal Status: |
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| Family: |
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First Claim:
Show all 20 claims |
What is claimed is:
1. An active terminating circuit comprising:
- a transmission line input for coupling to a transmission line;
- a sensing device, having a gate coupled to the transmission line input, for driving a back node;
- a first capacitor, coupled between the back node and a p-gate node;
- a p-channel clamping transistor, having a gate coupled to the p-gate node, for driving the transmission line with a first clamping current when activated by the sensing device;
- a pullup device, coupled between the p-gate node and a power-supply voltage, for biasing the p-gate node to the power-supply voltage;
- a second capacitor, coupled between the back node and an n-gate node;
- an n-channel clamping transistor, having a gate coupled to the n-gate node, for driving the transmission line with a second clamping current when activated by the sensing device; and
- a pulldown device, coupled between the n-gate node and a ground voltage, for biasing the n-gate node to the ground voltage,
whereby the sensing device activates the first or second clamping currents to actively terminate the transmission line.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 17 U.S. patent(s) that reference this one
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