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 Title: |
US6413802:
Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Hu, Chenming; Alamo, CA
King, Tsu-Jae; Fremont, CA
Subramanian, Vivek; Redwood City, CA
Chang, Leland; Berkeley, CA
Huang, Xuejue; Albany, CA
Choi, Yang-Kyu; Albany, CA
Kedzierski, Jakub Tadeusz; Hayward, CA
Lindert, Nick; Berkeley, CA
Bokor, Jeffrey; Oakland, CA
Lee, Wen-Chin; Beaverton, OR
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| Assignee: |
The Regents of the University of California, Oakland, CA
other patents from UNIVERSITY OF CALIFORNIA, THE REGENTS OF (599425) (approx. 4,840)
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| Published / Filed: |
2002-07-02
/ 2000-10-23
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| Application Number: |
US2000000695532
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| IPC Code: |
Advanced:
H01L 21/336;
H01L 21/84;
H01L 27/12;
H01L 29/786;
Core:
H01L 21/02;
H01L 21/70;
H01L 29/66;
more...
IPC-7:
H01L 21/00;
H01L 21/84;
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| ECLA Code: |
H01L29/78S; H01L21/336S2; H01L21/84; H01L27/12B;
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| U.S. Class: |
Current:
438/151;
257/E21.703;
257/E27.112;
438/283;
Original:
438/151;
438/283;
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| Field of Search: |
438/151,157,201,223,241,258,279,283,437,588,594,259,270,303,305,589,592
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| Government Interest: |
STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT
The U.S. government has rights to the invention pursuant to DARPA Contract No. N66001-97-1-8910 with the University of California.
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| Priority Number: |
| 2000-10-23 |
US2000000695532 |
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| Abstract: |
A FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.
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| Attorney, Agent or Firm: |
Townsend and Townsend and Crew LLP ;
Woodward, Henry K. ;
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| Primary / Asst. Examiners: |
Nelms, David; Dang, Phuc T.
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 28 claims |
What is claimed is:
1. A method of fabricating a double gate MOSFET device comprising the steps of:
- a) providing a silicon on insulator (SOI) substrate with a first silicon layer overlying an insulating layer and having an exposed major surface,
- b) providing an etchant mask on the major surface,
- c) patterning the etchant mask to define source, drain, and channel regions and expose surrounding portions of the silicon layer,
- d) etching the exposed silicon layer and forming source, drain, and channel regions extending from the insulator layer, the channel being a fin with a top surface and two opposing sidewalls,
- e) forming a gate dielectric on sidewalls of the channel region,
- f) depositing gate material over the etchant mask and the gate dielectric,
- g) selectively masking and etching the gate material to form a gate on the top surface and sidewalls of the channel region and separated from the channel region by the gate dielectric and the etchant mask,
- h) forming dielectric spacers between the gate and the source and drain regions, and
- i) doping the source and drain regions.
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| Background / Summary: |
Show background / summary
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| Drawing Descriptions: |
Show drawing descriptions
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| Description: |
Show description
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| Forward References: |
Show 279 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other Abstract Info: |
CHEMABS 137(04)055975Z
CHEMABS 137(04)055975Z
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| Other References: |
V. Subramanian et al., "A Bulk-Si-compatible Ultrathin-body SOI Technology for sub-100nm MOSFETS," Proceedings of the 57th Annual Device Research Conference, pp. 28-29 (1999).
Hisamoto et al., "A Folded-channel MOSFET for Deep-sub-tenth Micron Era," 1998 IEEE International Electron Device Meeting Technical Digest, pp. 1032-1034 (1998).
Huang et al., "Sub 50-nm FinFET: PMOS," 1999 IEEE International Electron Device Meeting Technical Digest, pp. 67-70 (1999).
Auth et al., Vertical, Fully-Depleted, Surrounding Gate MOSFETS on sub-0.1µm Thick Silicon Pillars, 1996 54th Annual Device Research Conference Digest, pp. 108-109 (1996).
Hisamoto et al., "A Fully Depleted Lean-Channel Transistor (DELTA)--A Novel Vertial Ultrathin SOI MOSFET," IEEE Electron Device Letters, v. 11(1), pp. 36-38 (1990).
(3 pages)
Cited by 31 patents
Leobandung et al., "Wire-channel and wrap-around-gate metal-oxide-semiconductor field-effect transistors with a significant reduction of short channel effects," J. Vac. Sci. Technol. B 15(6), pp. 2791-2794 (1997).
(4 pages)
Cited by 17 patents
[ISI abstract]
Auth et al., Vertical, Fully-Depleted, Surrounding Gate MOSFETS on sub-0.1µm Thick Silicon Pillars, 1996 54th Annual Device Research Conference Digest, pp. 108-109 (1996).
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