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 Title: |
US6417829:
Multisync display device and driver
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Jung, Byung-Hoo; Seoul, Republic of Korea
Lee, Ho-Hyeong; Seoul, Republic of Korea
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| Assignee: |
Samsung Electronics Co., Ltd., Suwon, Republic of Korea
other patents from SAMSUNG ELECTRONICS CO., LTD. (491065) (approx. 12,932)
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| Published / Filed: |
2002-07-09
/ 2000-06-02
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| Application Number: |
US2000000585430
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| IPC Code: |
Advanced:
G02F 1/133;
G09G 3/20;
G09G 3/36;
G09G 5/00;
Core:
more...
IPC-7:
G09G 3/36;
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| ECLA Code: |
G09G5/00T2; G09G3/36C12A; G09G3/36C14A; S09G5/00T4; S09G227/02A; S09G227/02B; S09G227/04B;
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| U.S. Class: |
345/098;
345/100;
345/213;
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| Field of Search: |
345/098,100,213
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| Priority Number: |
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| Abstract: |
The present invention modifies LCD panel display modes with a simple circuit configuration. When a driving frequency is supplied that does not drive all the configured pixels, the present invention drives all the pixels according to a multisync mode. The present invention comprises a LCD panel including a plurality of gate lines, a plurality of data lines, and a plurality of TFTs each having a gate electrode connected to the gate line and having a source electrode connected to the data line; a data driver receiving four driving clock signals and performing a multisync function on the driving frequency; a gate driver receiving four shift clock signals and performing multisync function on the driving frequency; and a timing controller outputting four driving clock signals and shift clocks and changing and outputting the status of the four driving clock signal and the shift clocks according to the normal mode or multisync mode.
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| Attorney, Agent or Firm: |
McGuireWoods LLP ;
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| Primary / Asst. Examiners: |
Hjerpe, Richard; Nguyen, Jennifer T.
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Family: |
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First Claim:
Show all 40 claims |
What is claimed is:
1. A liquid crystal display device, comprising:
- a liquid crystal display panel including a gate line, a data line and a thin-film transistor with a gate electrode connected to the gate line and a source electrode connected to the data line;
- a timing controller that outputs a first clock signal, a second clock signal that is an inversion of the first clock signal, a third clock signal, and a fourth clock signal that is an inversion of the third clock signal, wherein said timing controller changes outputting clock signals depending on an operation mode;
- a data driver supplying per line a gray image voltage through the data lines; and
- a gate driver including a first block and a second block, wherein the first block has a number of serially connected latch blocks and receives the first clock signal and the second clock signal, and the second block has a number of serially connected latch blocks and receives the third clock signal and the fourth clock signal, and wherein, in a multisync mode, said gate driver concurrently outputs a plurality of gate driving signals to a plurality of gate lines for a period according to the number of latch blocks.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 5 U.S. patent(s) that reference this one
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