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 Title: |
US6426662:
Twisted-ring oscillator and delay line generating multiple phases using differential dividers and comparators to match delays
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Arcus, Christopher G.; San Jose, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2002-07-30
/ 2001-11-12
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| Application Number: |
US2001000683040
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| IPC Code: |
Advanced:
H03K 3/0231;
H03K 3/03;
H03K 5/13;
H03L 7/081;
H03L 7/099;
H03K 5/00;
Core:
H03K 3/00;
more...
IPC-7:
G06F 1/04;
H03K 3/00;
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| ECLA Code: |
H03K3/0231; H03K3/03; H03K3/03D2; H03K5/13D; H03L7/081A; H03L7/099C;
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| U.S. Class: |
Current:
327/295;
327/274;
331/057;
Original:
327/295;
327/274;
331/057;
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| Field of Search: |
327/291,295,149,158,274,280,287
331/057
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| Priority Number: |
| 2001-11-12 |
US2001000683040 |
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| Abstract: |
A phase-locked loop (PLL) or a delay-locked loop (DLL) has differential delay stages with differential outputs driving differential clock inputs to a pair of differential toggle flip-flops. One flip-flop changes state on the rising edge and the other on the falling edge of the true output from the delay stage. Differential-to-single-ended buffers convert differential flip-flop outputs to single-ended multi-phase clocks. To avoid erratic or multiple oscillation and overtones, fewer than eight and preferably four differential delay stages are used. The delay stages are arranged in a twisted-ring with the differential outputs of the last delay stage crossed over and fed back to the differential inputs of the first delay stage. Tail currents of the delay stages can be adjusted by a voltage generated by a PLL loop. The differential toggle flip-flops allow for many taps or clock phases to be generated from the few delay stages.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Cunningham, Terry D.; Tra, Quan
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 20 claims |
What is claimed is:
1. A multi-phase clock generator comprising:
- a plurality of delay stages, each delay stage generating a true delay output and a complement delay output in response to a true input and a complement input;
- a pair of differential toggle flip-flops attached to each delay stage including a first flip-flop receiving the true delay output at a positive-clock input and receiving the complement delay output at a negative-clock input, the first flip-flop changing a state of a true output and a complement output when a rising edge of the true delay output and a falling edge of the complement delay output occurs;
- a second flip-flop receiving the complement delay output at a positive-clock input and receiving the true delay output at a negative-clock input, the second flip-flop changing a state of a true output and a complement output when a rising edge of the complement delay output and a falling edge of the true delay output occurs; and
- a plurality of buffers, each buffer receiving a true output and a complement output from either a first flip-flop or from a second flip-flop in the pair of differential toggle flip-flops for a delay stage, each buffer outputting an output clock generated from the true and complement outputs;
- wherein a plurality of the output clocks are generated by the buffers, the output clocks being delayed by different phases but having a same output period, whereby multiple phases of output clocks are generated using differential flip-flops.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 14 U.S. patent(s) that reference this one
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