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 Title: |
US6429678:
Capacitively-coupled extended swing zero-DC-power active termination with CMOS overshoot/undershoot clamps
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Wong, Anthony Yap; Cupertino, CA
Lin, Kwong Shing; Sunnyvale, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2002-08-06
/ 2001-11-21
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| Application Number: |
US2001000683127
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| IPC Code: |
Advanced:
H03K 17/16;
Core:
more...
IPC-7:
H03K 17/16;
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| ECLA Code: |
H04L25/02K11;
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| U.S. Class: |
326/030;
326/083;
326/086;
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| Field of Search: |
326/026,27,30,83,86,88
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| Priority Number: |
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| Abstract: |
An active terminating circuit has buffers to produce wider voltage drives on clamping transistors. A transmission line drives coupling capacitors. One capacitor drives an upper node that drives the gate of an upper buffer transistor. The upper buffer transistor drives a p-gate node coupled to a gate of a p-channel clamping transistor. The other capacitor drives a lower node that drives the gate of a lower buffer transistor, which drives an n-gate node of an n-channel clamping transistor. The drains of the clamping transistors are connected to the transmission line. Resistors pull the lower node to the power-supply voltage and pull the upper node to ground when no transitions occur on the transmission line, achieving zero standby power. When a transition is detected, it is coupled through the capacitors and buffered to the p-gate and n-gate nodes. Limiting transistors limit upper and lower node swings.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Le, Don Phu;
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| INPADOC Legal Status: |
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| Parent Case: |
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation-in-part (CIP) of the co-pending application for Zero DC-Power Active Termination with CMOS Overshoot and Undershoot Clamps, U.S. Ser. No. 09/681,344, filed Mar. 22, 2001.
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| Family: |
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First Claim:
Show all 20 claims |
What is claimed is:
1. A buffered active terminating circuit comprising:
- a pullup clamping transistor for sourcing an upper clamping current to a transmission node in response to an upper gate node;
- an upper coupling capacitor for coupling a voltage transition on the transmission node to an upper node;
- an upper buffer, having the upper node as an input, for driving an upper enabling voltage onto the upper gate node in response to a high-going transition on the transmission node, the upper enabling voltage enabling the pullup clamping transistor to source the upper clamping current;
- a pulldown clamping transistor for sinking a lower clamping current from a transmission node in response to a lower gate node;
- a lower coupling capacitor for coupling the voltage transition on the transmission node to a lower node; and
- a lower buffer, having the lower node as an input, for driving a lower enabling voltage onto the lower gate node in response to a low-going transition on the transmission node, the lower enabling voltage enabling the pulldown clamping transistor to sink the lower clamping current,
- whereby clamping currents are applied to the transmission node.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
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