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Title: US6442669: Architecture for a process complex of an arrayed pipelined processing engine
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Country: US United States of America

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18 pages

 
Inventor: Wright, Michael L.; Raleigh, NC
Kerr, Darren; Palo Alto, CA
Key, Kenneth Michael; Raleigh, NC
Jennings, William E.; Cary, NC

Assignee: Cisco Technology, Inc., San Jose, CA
other patents from CISCO TECHNOLOGY, INC. (739062) (approx. 785)
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Published / Filed: 2002-08-27 / 2000-11-30

Application Number: US2000000727068
IPC Code: Advanced: G06F 15/78;
Core: G06F 15/76;
IPC-7: G06F 15/00;

ECLA Code: G06F15/78V;

U.S. Class: 712/019; 710/052;

Field of Search: 712/010-22,52-57 710/052

Priority Number:
2000-11-30  US2000000727068
1998-06-29  US1998000106436

Abstract: A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient "context" data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.

Attorney, Agent or Firm: Cesari and McKenna, LLP ;

Primary / Asst. Examiners: Follansbee, John A.;

Maintenance Status: CC Certificate of Correction issued
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Related Applications: Go to Result Set: 2 patent(s) that list this one as related
Application Number Filed Patent Pub. Date  Title
US1998000106436 1998-06-29    2001-02-27  Method and apparatus for passing data among processor complex stages of a pipelined processing engine


       
Parent Case:

CROSS-REFERENCE TO RELATED APPLICATIONS
    This application is a continuation of U.S. patent application Ser. No. 09/106,436, filed Jun. 29, 1998 now U.S. Pat. No. 6,195 739, entitled "Method and Apparatus for Passing Data Among Processor Complex Stages of a Pipelined Processing Engine." The entirety of said copending application is hereby incorp by reference.
    This invention is related to the following U.S. Patent Applications:
  • U.S. patent application Ser. No. (09/106,478) titled, PROGRAMMABLE ARRAYED PROCESSING ENGINE ARCHITECTURE FOR A NETWORK SWITCH;
  • U.S. patent application Ser. No. (09/106,244) titled, SYSTEM FOR CONTEXT SWITCHING BETWEEN PROCESSING ELEMENTS IN A PIPELINE OF PROCESSING ELEMENTS now U.S. Pat. No. 6,101,599; and
  • U.S. patent application Ser. No. (09/106,246) titled, SYNCHRONIZATION AND CONTROL SYSTEM FOR AN ARRAYED PROCESSING ENGINE now U.S. Pat. No. 6,119,215, each of which was filed on even date herewith and assigned to the assignee of the present invention.
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First Claim:
Show all 14 claims		 What is claimed is:     1. Apparatus for passing transient data among processor complex stages of a pipelined processing engine, each processor complex stage including a central processing unit (CPU), the apparatus comprising:
  • a pair of context memories storing the transient data for processing by the CPU;
  • data mover cooperatively coupled to the context memories to pass the transient data among the stages of the engine substantially simultaneously with the processing of the data by the CPU;
  • an instruction memory storing instructions used by the CPU to process the transient data;
  • a memory manager interconnecting the instruction memory, the context memories and the CPU, the memory manager mapping a contiguous address space viewed by the CPU to contents of the instruction memory and context memories;
  • wherein the memorv manager comprises a state machine that determines a current phase specifying one of first and second context memories used by the CPU to process data.
    •


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Forward References: Show 25 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (25)   |   Backward references (71)   |   Citation Link

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    • Continuity Data:
    Application Number Filed Notes
    US2000000727068 2000-11-30  is a related to the prior publication
         US20050125643A1 issued 2005-06-09  Architecture for a processor complex of an arrayed pipelined processing engine
    US2004000023283 2004-12-27  is a continuation of
    US2002000222277  2002-08-16   (granted)
         US6836838 issued 2004-12-28   Architecture for a processor complex of an arrayed pipelined processing engine
    11023283   is a continuation of
    US2002000222277  2002-08-16
         US6836838 issued 2004-12-28   Architecture for a processor complex of an arrayed pipelined processing engine
    US2002000222277 2002-08-16  is a continuation of
    >US2000000727068<  2000-11-30   (granted)
         US6442669 issued 2002-08-27   Architecture for a process complex of an arrayed pipelined processing engine
    US2002000222277   is a continuation of
    >US2000000727068<  2000-11-30
         US6442669 issued 2002-08-27 2002-08-27  Architecture for a process complex of an arrayed pipelined processing engine
    >US2000000727068< 2000-11-30  is a continuation of
    US1998000106436  1998-06-29   (pending) [presumed granted]
         US6195739 issued 2001-02-27   Method and apparatus for passing data among processor complex stages of a pipelined processing engine
    >US2000000727068< 2000-11-30  is a continuation of
    US1998000106436  1998-06-29   (granted)
         US6195739 issued 2001-02-27   Method and apparatus for passing data among processor complex stages of a pipelined processing engine
    >US2000000727068<   is a continuation of
    US1998000106436  1998-06-29
         US6195739 issued 2001-02-27 2001-02-27  Method and apparatus for passing data among processor complex stages of a pipelined processing engine


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