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Title: US6483736: Vertically stacked field programmable nonvolatile memory and method of fabrication
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Country: US United States of America

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Inventor: Johnson, Mark G.; Los Altos, CA
Lee, Thomas H.; Cupertino, CA
Subramanian, Vivek; Menlo Park, CA
Farmwald, Paul Michael; Portola Valley, CA
Cleeves, James M.; Redwood City, CA

Assignee: Matrix Semiconductor, Inc., Santa Clara, CA
other patents from MATRIX SEMICONDUCTOR, INC. (765549) (approx. 49)
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Published / Filed: 2002-11-19 / 2001-08-24

Application Number: US2001000939431

IPC Code: Advanced: G11C 11/56; G11C 17/14; G11C 17/16; H01L 27/102;
Core: more...
IPC-7: G11C 11/00;

ECLA Code: H01L27/102D; G11C11/56R; G11C17/14; G11C17/16;

U.S. Class: Current: 365/130; 257/E27.073; 365/164;
Original: 365/130; 365/164;

Field of Search: 365/103,164,114,120,130

Priority Number:
2001-08-24  US2001000939431
2000-11-15  US2000000714440
1999-12-22  US1999000469658
1998-11-16  US1998000192883

Abstract:     A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Attorney, Agent or Firm: Brinks Hoffer Gilson & Lione ;

Primary / Asst. Examiners: Nelms, David; Le, Thong

Maintenance Status: CC Certificate of Correction issued
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Related Applications: Go to Result Set: 5 patent(s) that list this one as related
Application Number Filed Patent Pub. Date  Title
US2000000714440 2000-11-15       
US1999000469658 1999-12-22    2001-02-06  Vertically stacked field programmable nonvolatile memory and method of fabrication
US1998000192883 1998-11-16    2000-03-07  Vertically stacked field programmable nonvolatile memory and method of fabrication


       
Parent Case:     This application is a continuation of application Ser. No. 09/714,440, filed Nov. 15, 2000, pending, which is a continuation of application Ser. No. 09/469,658, filed Dec. 22, 1999, now U.S. Pat. No. 6,185,122, which is a divisional of application Ser. No. 09/192,883, filed Nov. 16, 1998, now U.S. Pat. No. 6,034,882, which is hereby incorporated by reference herein.

Designated Country: AE AL AM AP AT AZ BA BB BG BR BY CA CH CU CZ DK EA EE ES FI GD GE GH GM HR HU ID IL IN IS KE KG KP  DE FR GB 

Family: Show 36 known family members

First Claim:
Show all 20 claims
We claim:     1. A 3-dimensional memory array built above a substrate, the memory array comprising:
  • N layers of memory cells;
  • N+1 layers of conductors;
  • said memory cells and conductors fabricated using no more than N+1 masks.


Background / Summary: Show background / summary

Drawing Descriptions: Show drawing descriptions

Description: Show description

Forward References: Show 92 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (92)   |   Backward references (129)   |   Citation Link

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Other Abstract Info: DERABS G2000-246114

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  • Continuity Data:
    Application Number Filed Notes

    US2001000939431 2001-08-24  is a related to the prior publication
         US20050063220A1 issued 2005-03-24  Memory device and method for simultaneously programming and/or reading memory cells on different levels

    US2001000939431 2001-08-24  is a related to the prior publication
         US20050105371A1 issued 2005-05-19  Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement

    US2005000987091   is a continuation of
    US2004000774818  2004-02-09   (pending) [presumed granted]
         US7190602 issued 2007-03-13   Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement

    US2004000987091 2004-11-12  is a continuation of
    US2004000774818  2004-02-09   (pending) [presumed granted]
         US7190602 issued 2007-03-13   Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement

    US2004000774818 2004-02-09  is a continuation of
    US2002000253354  2002-09-23   (granted)
         US6780711 issued 2004-08-24   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2004000774818   is a continuation of
    US2002000253354  2002-09-23
         US6780711 issued 2004-08-24   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2002000253354 2002-09-23  is a continuation of
    >US2001000939431<  2001-08-24   (granted)
         US6483736 issued 2002-11-19   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2002000253354   is a continuation of
    >US2001000939431<  2001-08-24
         US6483736 issued 2002-11-19   Vertically stacked field programmable nonvolatile memory and method of fabrication

    >US2001000939431< 2001-08-24  is a continuation of
    US2000000714440  2000-11-15   (pending) [presumed granted]
         US6351406 issued 2002-02-26   Vertically stacked field programmable nonvolatile memory and method of fabrication

    >US2001000939431< 2001-08-24  is a continuation of
    US2000000714440  2000-11-15   (granted)
         US6351406 issued 2002-02-26   Vertically stacked field programmable nonvolatile memory and method of fabrication

    >US2001000939431<   is a continuation of
    US2000000714440  2000-11-15
         US6351406 issued 2002-02-26   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2000000714440 2000-11-15  is a continuation of
    US1999000469658  1999-12-22   (granted)
         US6185122 issued 2001-02-06   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2000000714440   is a continuation of
    US1999000469658  1999-12-22
         US6185122 issued 2001-02-06   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US1999000469658 1999-12-22  is a division of
    US1998000192883  1998-11-16   (granted)
         US6034882 issued 2000-03-07   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US1999000469658   is a division of
    US1998000192883  1998-11-16
         US6034882 issued 2000-03-07   Vertically stacked field programmable nonvolatile memory and method of fabrication


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