Other References: |
John H. Douglas, "The Route to 3-D Chips", High Technology, 3, No. 9, 55-59 (1983).
Kawashima et al., "A Charge-Transfer Amplifier and an Encoded-Bus Architecture for Low-Power SRAM's", IEEE Journal of Solid-State Circuits, 33, No. 5, 793-799 (1998).
(7 pages)
Cited by 18 patents
[ISI abstract]
Cappelleti et al., "Flash Memories", Kluwer Academic Publishers, Table of Contents, pp. 47, pp. 308 (1999).
"Three-Dimensional Read-Only Memory (3D-ROM)" [online] [retrieved on Aug. 10, 2000] retrieved from the Internet: <URL: http://sites.netscape.net/zhangpatents/3D-ROM/3D-ROM.htm.
Semiconductor International, "3D-ROM-A First Practical Step Towards 3D-IC" [online] [retrieved on Aug. 10, 2000] retrieved from the Internet: <URL: http://www.semiconductor.net/semiconductor/Issues/webexclusives/200.../ six00063DROM.as.
Akasaka, Yoichi, " Three-Dimensional Integrated Circuit: Technology and Application Prospect," Microelectronics Journal, vol. 20 No. 1-2, 1989, pp. 105-111.
Akasaka, Yoichi, " Three-Dimensional IC Trends," Proceedings of the IEEE, vol. 74, No. 12, Dec. 1986, pp. 1703-1714.
(12 pages)
Cited by 74 patents
Bertin, Claude L., "Evaluation of a Three-Dimensional Memory Cube System," IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 16, No. 8, Dec. 1993, 1006-1011.
(6 pages)
Cited by 27 patents
[ISI abstract]
Camperi-Ginestet, C., " Vertical Electrical Interconnection of Compound Semiconductor Thin-Film Devices to Underlying Silicon Circuitry," IEEE Photonics Technology Letters, vol. 4, No. 9, Sep. 1992, pp. 1003-1006.
(4 pages)
Cited by 26 patents
[ISI abstract]
Hayashi, Y., "A New Three Dimensional IC Fabrication Technology, Stacking Thin Film Dual CMOS Layers," IEDM 1991, pp. 657-660.
Hayasky, Fumihiko, "A Self-Aligned Split-Gate Flash EEPROM Cell with 3-D Pillar Structure" 1999 Symposium on VLSI Technology Digest of Technical Papers, pp. 87-88.
"3-D Chip-on-Chip Stacking," Industry News, Semiconductor International, Dec. 1991.
Inoue, Y., "A Three-Dimensional Static RAM," IEEE Electron Device Letters, vol. Edl.-7, No. 5, May 1986, pp. 327-329.
(3 pages)
Cited by 25 patents
Jokerst, N.M., "Manufacturable Multi-Material Integration Compound Semiconductor," SPIE-The International Society for Optical Engineering, vol. 2524, Jul. 11-12, 1995, pp. 152-163.
Kurokawa, Takakazu, "3-D VLSI Technology in Japan and an Example: A Syndrome Decoder for Double Error Correction," Future Generations Computer Systems 4, No. 2, Sep. 1988, pp. 145-155.
Lay, Richard W., "TRW Develops Wireless Multiboard Interconnect System," Electronic Engineering Times, Nov. 5, 1984.
Maliniak, David, "Memory-Chip Stacks Send Density Sykward," Electronic Design 42, No. 17, Aug. 22, 1994, pp. 69-75.
Cited by 11 patents
[ISI abstract]
Pein, Howard, et al., "Performance of the 3-D PENCIL FLash EPROM Cell and Memory Array," IEEE Transactions on Electron Devices, vol. 42, No. 11, Nov. 1995, pp. 1982-1991.
Reber, M., et al., "Benefits of Vertically Stacked Integrated Circuits for Sequential Logic," IEEE 1996, pp. 121-124.
Sakamoto, Koji, "Architecture of Three Dimensional Devices," Bulletin of the Electrotechnical Laboratory, vol. 51, No. 1, 1987, pp. 16-29.
Schlaeppi, H.P., "Microsecond Core Memories Using Multiple Coincidence," 1960 International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 11, 1960, pp. 54-55.
Schlaeppi, H.P., "Microsecond Core Memories Using Multiple Coincidence," IRE Transactions on Electronic Computers, Jun., 1960, pp. 192-198.
Stacked Memory Modules, , IBM Technical Disclosure Bulletin, May 1995, pp. 433-434.
Stern, Jon M., "Design and Evaluation of an Epoxy Three-Dimensional Multichip Module," IEEE Transactions on Components, Packaging, and Manufacturing Technology--Part B, vol. 19, No. 1, Feb. 1996, pp. 188-194.
(7 pages)
Cited by 25 patents
[ISI abstract]
Terrill, Rob, "3D Packaging Technology Overview and Mass Memory Applications," IEEE 1996, pp. 347-355.
Thakur, Shashidhar, "An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing," IEEE 1995, pp. 207-210.
Watanabe, H., "Stacked Capacitor Cells for High-Density Dynamic RAMs," IEDM 1988, pp. 600-603.
Yamazaki, K., " Fabrication Technologies For Dual 4-KBIT stacked SRAM," IEDM 1986, pp. 435-438.

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