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 Title: |
US6493858:
Method and system for displaying VLSI layout data
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Solomon, Jeffrey M.; Millbrae, CA
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| Assignee: |
The Board of Trustees of the Leland Stanford Jr. University, Stanford, CA
other patents from STANFORD UNIVERSITY (675809) (approx. 1,667)
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| Published / Filed: |
2002-12-10
/ 2001-07-10
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| Application Number: |
US2001000901028
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| IPC Code: |
Advanced:
G06F 17/50;
G06T 17/40;
Core:
more...
IPC-7:
G06F 17/50;
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| ECLA Code: |
G06F17/50L; G06T17/40;
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| U.S. Class: |
716/011;
716/003;
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| Field of Search: |
716/011,3
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| Priority Number: |
| 2001-07-10 |
US2001000901028 |
| 2001-03-23 |
US2001000278001P |
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| Abstract: |
A VLSI layout editor and method for using same that increases display and re-display speed and accuracy uses properties inherent to VLSI layouts that allows them to be displayed efficiently and accurately independent of the canonical expression of the VLSI design. The VLSI layout editor and methods for using same use precomputed images that each represent a portion of the VLSI layout, a hierarchy cache that includes multiple LOD versions of selected sub-designs in the pre-computed images, and selected direct determination of the viewable representation from the canonical expression for at least one LOD. Apparatus and methods according to the present invention can render a particular type of data whose canonical form is smaller than its corresponding displayed image thereof when the displayed image has geometric properties that allow heuristics and rasterization for dynamic and accurate expansion using selected combined techniques. Texture mapping and mipmapping can be used to accurately reduce, expand and reorder layers in a viewable image expanded from a canonical expression of the VLSI layout.
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| Attorney, Agent or Firm: |
Fleshner & Kim, LLP ;
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| Primary / Asst. Examiners: |
Tran, M.;
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| INPADOC Legal Status: |
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| Parent Case: |
This application claims priority to U.S. Provisional Application Ser. No. 60/278,001, filed Mar. 23, 2001, whose entire disclosure is incorporated herein by reference, and is subject to a contract made by Defense Advanced Research, Contract No. RFP-MOA904-98-R-5855.
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| Family: |
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First Claim:
Show all 20 claims |
What is claimed is:
1. A VLSI layout editor, comprising:
- a first memory that stores a canonical expression of a VLSI layout having a plurality of layers; and
- a display controller coupled to the first memory that generates a displayable representation of ordered layers of the VLSI layout that tracks changes in a user viewpoint, wherein the displayable representation comprises a precomputed image that represents a portion of the VLSI layout, and wherein the precomputed image is used in two or more user viewpoints.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 14 U.S. patent(s) that reference this one
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