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 Title: |
US6501307:
Spread-spectrum clock buffer/driver that modulates clock period by switching loads
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Yen, Yao Tung; Cupertino, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2002-12-31
/ 2001-11-12
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| Application Number: |
US2001000683041
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| IPC Code: |
Advanced:
H03K 5/13;
H04B 15/04;
H03K 5/00;
Core:
H04B 15/02;
more...
IPC-7:
H03B 19/00;
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| ECLA Code: |
H03K5/13D2; H04B15/04;
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| U.S. Class: |
327/113;
327/114;
327/175;
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| Field of Search: |
327/261,262,263,264,276,277,278,281,113,114,172,175,173,174,176
377/047,48
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| Priority Number: |
| 2001-11-12 |
US2001000683041 |
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| Abstract: |
A clock modulator spreads the frequency spectrum of an input clock to generate an output clock. A capacitor is connected to an intermediate clock node by a load-switching transistor. When the transistor is turned on, the capacitor increases the loading on the intermediate clock node, increasing delay. When the transistor is turned off, the delay is reduced. Output clock cycle periods are extended when delay is added, and reduced when the transistor turns off. A counter or sequencer is clocked by the input clock and drives the load-switching transistor. The transistor is turned on and off for alternate cycles when the counter is a toggle flip-flop, spreading the frequency over two frequencies every two clock cycles. Two capacitors of different sizes, connected to the intermediate clock node by two transistors, can be switched by a 2-bit sequencer, spreading the output clock over 7 frequencies every 7 clock cycles.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Lam, Tuan T.;
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 20 claims |
What is claimed is:
1. A clock modulator for spreading a frequency spectrum of an input clock to generate an output clock with a varying frequency comprising:
- an input buffer, receiving the input clock, for driving an intermediate node;
- an output buffer, receiving the intermediate node, for driving the output clock;
- a load capacitor;
- a load switch for connecting the load capacitor to the intermediate node in response to a control signal and for disconnecting the load capacitor from the intermediate node in response to an inverse of the control signal; and
- a sequencer, responsive to the input clock, for sequencing the control signal through a predetermined sequence of states;
- wherein a clock period of the output clock is extended when the load switch connects the load capacitor to the intermediate node in response to a change in state of the control signal;
- wherein the clock period of the output clock is reduced when the load switch disconnects the load capacitor from the intermediate node in response to a change in state of the control signal,
- whereby frequency is modulated by extending the clock period when the load capacitor is connected, and reducing the clock period when the load capacitor is disconnected.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 21 U.S. patent(s) that reference this one
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