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 Title: |
US6513109:
Method and apparatus for implementing execution predicates in a computer processing system
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Gschwind, Michael K.; Danbury, CT
Sathaye, Sumedh; Fishkill, NY
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| Assignee: |
International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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| Published / Filed: |
2003-01-28
/ 1999-08-31
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| Application Number: |
US1999000387220
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| IPC Code: |
Advanced:
G06F 9/00;
G06F 9/30;
G06F 9/32;
G06F 9/38;
Core:
more...
IPC-7:
G06F 9/00;
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| ECLA Code: |
G06F9/38E2D; G06F9/30R4S; G06F9/32C; G06F9/38E2;
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| U.S. Class: |
712/200;
712/233;
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| Field of Search: |
712/200,220,233,23
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| Priority Number: |
| 1999-08-31 |
US1999000387220 |
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| Abstract: |
There is provided a method for executing an ordered sequence of instructions in a computer processing system. The sequence of instructions is stored in a memory of the system. At least one of the instructions includes a predicated instruction that represents at least one operation that is to be conditionally performed based upon an associated flag value. The method includes the step of fetching a group of instructions from the memory. Execution of instructions are scheduled within the group, wherein the predicated instruction is moved from its original position in the ordered sequence of instructions to an out-of-order position in the sequence of instructions. The instructions are executed in response to the scheduling. In one embodiment of the invention, the method further includes generating a predicted value for the associated flag value, when the associated flag value is not available at execution of the predicated instruction. In another embodiment, the method further includes modifying execution of the operations represented by the predicated instruction based upon the predicted value. In yet another embodiment, the modifying step includes selectively suppressing either the execution or write back of results generated by the operations represented by the predicated instruction based upon the predicted value. In still another embodiment, the method includes predicting a data dependence relationship of an instruction with a previous predicated instruction or another previous instruction. The correctness of the relationship prediction may be verified, and a selection may be made from among a number of predicted dependencies.
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| Attorney, Agent or Firm: |
F. Chau & Associates, LLP ;
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| Primary / Asst. Examiners: |
Coleman, Eric;
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| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
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| Family: |
Show 5 known family members
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First Claim:
Show all 35 claims |
What is claimed is:
1. A method for executing an ordered sequence of instructions in a computer processing system, the sequence of instructions stored in a memory of the system, wherein at least one of the instructions comprises a predicated instruction that represents at least one operation that is to be conditionally performed based upon an associated flag value, the method comprising the steps of:
- fetching a group of instructions from the memory;
- scheduling execution of instructions within the group, wherein the predicated instruction is moved from its original position in the ordered sequence of instructions to an out-of-order position in the sequence of instructions; and
- executing the instructions in response to said scheduling.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 19 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other Abstract Info: |
DERABS G2001-479550
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| Other References: |
Mahlke et al., "Sentinel Scheduling for VLIW and Superscalar Processors", Proceedings of the 5th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 1992.
Park et al., "On Predicated Execution", Tech. Rep. HPL-91-58, HP Laboratories, Palo Alto, CA, May 1991.
Rau, et al., "The Cydra 5 Departmental Supercomputer Design Philosophies, Decisions, and Trade-offs", IEEE Computer Society, vol. 22, No. 1, Jan. 1989.
David C. Lin, "Compiler Support For Predicated Execution In Superscalar Processors", Thesis, Master of Science in Electrical Engineering, Graduate College, University of Illinois, 1990.
Mahlke et al., "Effective Compiler Support for Predicated Execution Using the Hyperblock", IEEE, Sep. 1992, pp. 45-54.
K. Ebcioglu, "Some Design Ideas for a VLIW Architecture for Sequential-Natured Software, Parallel Processing", Cosnard et al. (Editors), Proceedings of the IFIP WG 10.3 Working Conference on Parallel Processing, Pisa Italy, Apr. 25-27, 1988, pp. 3-21.
Ebcioglu et al., "Some Global Compiler Optimizations and Architectural Features for Improving Performance of Superscalars", Research Report, RC 16145 (#71759) Oct. 2, 1990, pp. 1-13.
Ebcioglu et al., "An Eight-Issue Tree-VLIW Processor for Dynamic Binary Translation" IEEE Feb. 1998, pp. 488-495.
Smith et al., "Implementing Precise Interrupts in Pipelined Processors", IEEE Transactions on Computers, vol. 37, No. 5, May 1988, pp. 562-573.
(12 pages)
Cited by 92 patents
Pnevmatikatos et al., "Guarded Execution and Branch Prediction in Dynamic ILP Processors", 21st International Symposium on Computer Architecture, Chicago, IL, 1994.
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