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Title: |
US6515888:
Low cost three-dimensional memory array
[ Derwent Title ]

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Country: |
US United States of America

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Inventor: |
Johnson, Mark G.; Los Altos, CA
Lee, Thomas H.; Cupertino, CA
Subramanian, Vivek; Redwood City, CA
Farmwald, P. Michael; Portola Valley, CA
Knall, N. Johan; Sunnyvale, CA

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Assignee: |
Matrix Semiconductor, Inc., Santa Clara, CA
other patents from MATRIX SEMICONDUCTOR, INC. (765549) (approx. 49)
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Published / Filed: |
2003-02-04
/ 2001-08-13

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Application Number: |
US2001000928969

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IPC Code: |
Advanced:
G11C 17/16;
H01L 27/10;
H01L 27/06;
Core:
G11C 17/14;
more...
IPC-7:
G11C 11/00;

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ECLA Code: |
G11C17/16;

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U.S. Class: |
Current:
365/130;
257/E27.026;
257/E27.071;
365/105;
365/113;
365/225.7;
Original:
365/130;
365/225.7;
365/113;
365/105;

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Field of Search: |
365/225.7,113,105,130

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Priority Number: |
| 2001-08-13 |
US2001000928969 |
| 2000-08-14 |
US2000000638428 |

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Abstract: |
A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).

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Attorney, Agent or Firm: |
Brinks Hofer Gilson & Lione ;

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Primary / Asst. Examiners: |
Hoang, Huan;

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INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report

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Foreign References: |

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Other References: |
Douglas, John H., "The Route To 3-D Chips", High Technology, Sep. 1983, vol. 3, No. 9, pp. 55-59.
Edited by Cappelletti, Paulo et al., "Flash Memories", Kluwer Academic Publishers, 1999.
Kawashima, Shoichiro et al., "A Charge-Transfer Amplifier and an Encoded-Bus Architecture for Low-Power SRAM's", IEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1998, pp. 793-799.
(7 pages)
Cited by 18 patents
[ISI abstract]
Zhang, Ph.D., Guobiao, "Three-Dimensional Read-Only Memory (3D-ROM)", presentation from website zhangpatents, pp. 1-29.
Zhang, Ph.D., Guobiao, "3D-ROM--A First Practical Step Towards 3D-IC" Semiconductor International, Jul. 2000, from website zhangpatents, pp. 1-7.

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Continuity Data: |
| Application Number | Filed | Notes |
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US2002000186359 | 2002-06-27 | is a
continuation in part of |
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>US2001000928969<
| 2001-08-13 |
(pending)
[presumed granted]
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US6515888 issued 2003-02-04 Low cost three-dimensional memory array
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>US2001000928969< | 2001-08-13 | is a
continuation in part of |
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US2000000638428
| 2000-08-14 |
(pending)
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>US2001000928969< | 2001-08-13 | is a
continuation in part of |
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US2000000638428
| 2000-08-14 |
(abandoned)
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