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Title: US6515888: Low cost three-dimensional memory array
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Country: US United States of America

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14 pages

 
Inventor: Johnson, Mark G.; Los Altos, CA
Lee, Thomas H.; Cupertino, CA
Subramanian, Vivek; Redwood City, CA
Farmwald, P. Michael; Portola Valley, CA
Knall, N. Johan; Sunnyvale, CA

Assignee: Matrix Semiconductor, Inc., Santa Clara, CA
other patents from MATRIX SEMICONDUCTOR, INC. (765549) (approx. 49)
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Published / Filed: 2003-02-04 / 2001-08-13

Application Number: US2001000928969

IPC Code: Advanced: G11C 17/16; H01L 27/10; H01L 27/06;
Core: G11C 17/14; more...
IPC-7: G11C 11/00;

ECLA Code: G11C17/16;

U.S. Class: Current: 365/130; 257/E27.026; 257/E27.071; 365/105; 365/113; 365/225.7;
Original: 365/130; 365/225.7; 365/113; 365/105;

Field of Search: 365/225.7,113,105,130

Priority Number:
2001-08-13  US2001000928969
2000-08-14  US2000000638428

Abstract:     A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).

Attorney, Agent or Firm: Brinks Hofer Gilson & Lione ;

Primary / Asst. Examiners: Hoang, Huan;

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Related Applications:
Application Number Filed Patent Pub. Date  Title
US2000000638428 2000-08-14       


       
Parent Case:

CROSS REFERENCE TO RELATED APPLICATION
    This application is a continuation-in-part of copending U.S. patent application Ser. No. 09/638,428, filed Aug. 14, 2000, the entirety of which is hereby incorporated by reference.

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First Claim:
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We claim:     1. A 3-dimensional memory array comprising a plurality of vertically-stacked layers of memory cells, each memory cell comprising a respective antifuse layer, and said memory cells characterized by an average maximum read current less than 500 microamperes when the respective antifuse layers are breached.

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Forward References: Show 42 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (42)   |   Backward references (19)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 12pp US4272880  1981-06 Pashley  Intel Corporation MOS/SOS Process
Buy PDF- 17pp US4442507  1984-04 Roesner  Burroughs Corporation Electrically programmable read-only memory stacked above a semiconductor substrate
Buy PDF- 14pp US4489478  1984-12 Sakurai  Fujitsu Limited Process for producing a three-dimensional semiconductor device
Buy PDF- 8pp US4498226  1985-02 Inoue et al.  Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing three-dimensional semiconductor device by sequential beam epitaxy
Buy PDF- 16pp US4499557  1985-02 Holmberg et al.  Energy Conversion Devices, Inc. Programmable cell for use in programmable electronic arrays
Buy PDF- 28pp US4646266  1987-02 Ovshinsky et al.  Energy Conversion Devices, Inc. Programmable semiconductor structures and methods for using the same
Buy PDF- 19pp US4677742  1987-07 Johnson  Energy Conversion Devices, Inc. Electronic matrix arrays and method for making the same
Buy PDF- 11pp US5070384  1991-12 McCollum et al.  Actel Corporation Electrically programmable antifuse element incorporating a dielectric and amorphous silicon interlayer
Buy PDF- 7pp US5306935  1994-04 Esquivel et al.  Texas Instruments Incorporated Method of forming a nonvolatile stacked memory
Buy PDF- 9pp US5427979  1995-06 Chang  VLSI Technology, Inc. Method for making multi-level antifuse structure
Buy PDF- 10pp US5441907  1995-08 Sung et al.  Taiwan Semiconductor Manufacturing Company Process for manufacturing a plug-diode mask ROM
Buy PDF- 25pp US5535156  1996-07 Levy et al.  California Institute of Technology Transistorless, multistable current-mode memory cells and memory arrays and methods of reading and writing to the same
Buy PDF- 18pp US5602987  1997-02 Harari et al.  SanDisk Corporation Flash EEprom system
Buy PDF- 21pp US5640343  1997-06 Gallagher et al.  International Business Machines Corporation Magnetic memory array using magnetic tunnel junction devices in the memory cells
Buy PDF- 25pp US5745407  1998-04 Levy et al.  California Institute of Technology Transistorless, multistable current-mode memory cells and memory arrays and methods of reading and writing to the same
Buy PDF- 23pp US5835396  1998-11 Zhang   Three-dimensional read-only memory
Buy PDF- 38pp US6034882  2000-03 Johnson et al.  Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
Buy PDF- 18pp US6236587  2001-05 Gudesen et al.   Read-only memory and read-only memory devices
Buy PDF- 9pp US20020027822A1  2002-03 Candelier et al.   ONE-TIME PROGRAMMABLE MEMORY CELL IN CMOS TECHNOLOGY
       
Foreign References:
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PDF
Publication Date IPC Code Assignee   Title
Buy PDF- 37pp WO9914763 1999-03  G11C 11/56 GUDESEN, HANS, GUDE A READ-ONLY MEMORY AND READ-ONLY MEMORY DEVICES 


Other References:
  • Douglas, John H., "The Route To 3-D Chips", High Technology, Sep. 1983, vol. 3, No. 9, pp. 55-59.
  • Edited by Cappelletti, Paulo et al., "Flash Memories", Kluwer Academic Publishers, 1999.
  • Kawashima, Shoichiro et al., "A Charge-Transfer Amplifier and an Encoded-Bus Architecture for Low-Power SRAM's", IEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1998, pp. 793-799. (7 pages) Cited by 18 patents [ISI abstract]
  • Zhang, Ph.D., Guobiao, "Three-Dimensional Read-Only Memory (3D-ROM)", presentation from website zhangpatents, pp. 1-29.
  • Zhang, Ph.D., Guobiao, "3D-ROM--A First Practical Step Towards 3D-IC" Semiconductor International, Jul. 2000, from website zhangpatents, pp. 1-7.


  • Continuity Data:
    Application Number Filed Notes

    US2002000186359 2002-06-27  is a continuation in part of
    >US2001000928969<  2001-08-13   (pending) [presumed granted]
         US6515888 issued 2003-02-04   Low cost three-dimensional memory array

    >US2001000928969< 2001-08-13  is a continuation in part of
    US2000000638428  2000-08-14   (pending)

    >US2001000928969< 2001-08-13  is a continuation in part of
    US2000000638428  2000-08-14   (abandoned)


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