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 Title: |
US6538519:
Phase-locked loop circuit
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Lo, Chi Wa; Tuen Mun, Hong Kong
Luong, Howard Cam; Clear Water Bay, Hong Kong
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| Assignee: |
The Hong Kong University of Science and Technology, Hong Kong, China
other patents from THE HONG KONG UNIVERSITY OF SCIENCE & TECHNOLOGY (722657) (approx. 55)
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| Published / Filed: |
2003-03-25
/ 2001-10-12
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| Application Number: |
US2001000977073
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| IPC Code: |
Advanced:
H03L 7/089;
H03L 7/099;
Core:
more...
IPC-7:
H03B 5/00;
H03L 7/085;
H03L 7/099;
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| ECLA Code: |
H03L7/089C2; H03L7/099;
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| U.S. Class: |
331/017;
331/036.C;
331/175;
331/177.V;
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| Field of Search: |
331/007,18,25,36 C,175,177 V
327/156-159
375/376
360/051
332/127
455/260
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| Priority Number: |
| 2001-10-12 |
US2001000977073 |
| 2000-10-12 |
US2000000240618P |
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| Abstract: |
A phase locked loop wherein the voltage controlled oscillator is controlled by the output of a phase comparison circuit through a split loop filter. The oscillator has two varactors in parallel in its tuning circuit. The first branch of the loop filter includes an integrator filter generating a first error voltage and the second branch includes a low pass filter generating a second error voltage. The first error voltage controls one varactor and the second error voltage controls the other varactor. As a result the error voltages are effectively summed in the capacitance domain to obviate the need for a dedicated error voltage adder and to allow the total capacitance required in the loop filter to be reduced while still retaining an adequate signal to noise ratio in the filter.
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| Attorney, Agent or Firm: |
Ostrolenk, Faber, Gerb & Soffen, LLP ;
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| Primary / Asst. Examiners: |
Mis, David C.;
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| INPADOC Legal Status: |
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| Parent Case: |
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority of Provisional Patent Application No. 60/240,618, filed on Oct. 12, 2000.
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| Family: |
Show 2 known family members
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First Claim:
Show all 4 claims |
We claim:
1. In a phase-locked loop wherein the signal of a voltage controlled oscillator is locked to a reference signal, and wherein said oscillator frequency is controlled by the output of a phase comparison circuit through a split loop filter, said filter including in one branch an integrator filter generating a first error voltage with respect to the reference and oscillator signals, and including in the second branch a low pass filter generating a second error voltage with respect to the reference and oscillator signals, the improvement comprising:
- first and second varactor elements connected in parallel in the tuning circuit of said voltage controlled oscillator to control the frequency of said oscillator, said first varactor element connected to the output of the integrator filter and said second varactor element connected to the output of the low pass filter.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 2 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other References: |
Mijuskovic, et al., Cell-Based Fully Integrated CMOS Frequency Synthesizers, Mar., 1994, pp. 271-279, vol. 29, No. 3, IEEE Journal of Solid-State Circuits.
(9 pages)
Cited by 12 patents
[ISI abstract]
Craninckx, et al., A Fully Integrated CMOS DCS-1800 Frequency Synthesizer, Dec. 1998, pp. 2054-2065, vol. 33, No. 12, IEEE Journal of Solid-State Circuits.
(12 pages)
Cited by 18 patents
[ISI abstract]
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