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Title: US6550046: Method for automated placement of cells in an integrated circuit layout
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Country: US United States of America

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10 pages

 
Inventor: Balasa, Florin; Tustin, CA
Lampaert, Koen; Laguna Beach, CA

Assignee: Conexant Systems, Inc., Newport Beach, CA
other patents from CONEXANT SYSTEMS, INC. (754454) (approx. 472)
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Published / Filed: 2003-04-15 / 1999-10-01

Application Number: US1999000411417

IPC Code: Advanced: G06F 17/50;
Core: more...
IPC-7: G06F 17/50;

ECLA Code: G06F17/50L1;

U.S. Class: 716/008; 716/002; 716/011;

Field of Search: 716/011,2,9,10,8 703/013

Priority Number:
1999-10-01  US1999000411417
1998-10-08  US1998000103509P

Abstract: An automated method for packing cells in the generation of an integrated circuit design layout that is especially useful for circuits having symmetry constraints, which is the case for most analog circuits, uses sequence pair encoding and simulated annealing. From the set of all cells needed to implement the circuit, subsets of the cells are defined that must exhibit symmetry. Symmetry constraints are defined for each subset and the cells are encoded as ordered sequence-pairs. To reduce the solution space, the initial sequence pair encoding is required to be symmetry-feasible and the annealer subspace is limited to symmetry-feasible sequence-pairs.

Attorney, Agent or Firm: Thomas, Kayden, Horstemeyer & Risley, LLP ;

Primary / Asst. Examiners: Niebling, John F.; Whitmore, Stacy A

INPADOC Legal Status: Show legal status actions

Parent Case:

CROSS REFERENCE TO RELATED APPLICATION
    This application claims priority from provisional application, Serial No. 60/103,509 filed Oct. 8, 1998.

Family: None

First Claim:
Show all 20 claims
What is claimed is:     1. A method for the automated packing of an integrated circuit layout having a plurality of cells, the method comprising the steps of:
  • identifying from the plurality of cells a subset of cells for which substantial symmetry is desired;
  • defining symmetry constraints for the subset;
  • encoding the packing of the cells as ordered sequence-pairs; and
  • optimizing the encoding using simulated annealing subject to the symmetry constraints.


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Forward References: Show 7 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (7)   |   Backward references (0)   |   Citation Link

       
Foreign References: None

Other References:
  • Bourai, "Symmetry detection for automatic analog layout recycling", IEEE Jan. 1999. pp. 5-8.*
  • Hatta, K. et al., "Solving the rectangular packing problem by an adaptive GA based on sequence-pair", Jan. 1999, IEEE, pp. 181-184.*
  • Murata, H. et al., "Rectangule-packing based module placement", Nov. 1995, IEEE, pp. 472-479.*
  • Malavasi, E. et al., "Automation of IC layout with analog constraints", Aug. 1996, IEEE, pp. 923-942.* (20 pages) [ISI abstract]
  • F. Balasa, K. Lampaert, "Module Placement for Analog Layout Using the Sequence-Pair Representation," Proc. 36th ACM/IEEE Design Automation Conf., pp. 274-279, New Orleans. LA, Jun. 1999.
  • Y.-X Pang, F. Balasa, K. Lampaert, C.-K. Cheng, "Block Placement with Symmetry Constraints Based on the O-Tree Non-Slicing Representation," Proc. 37th ACM/IEEE Design Automation Conf., pp. 464-467, Los Angeles CA, Jun. 2000.
  • F. Balasa, K. Lamaert, "Symmetry Within the Sequence-Pair Representation in the Context of Placement for Analog Design," IEEE Trans. On Comp.-Aided Design of Integrated Circuits and Systems, vol. 19, No. 7, pp. 721-731, Jul. 2000. (11 pages) Cited by 3 patents [ISI abstract]
  • F. Balasa, "Modeling Non-Slicing Floorplans with Binary Trees," Proc. IEEE Int. Conf. Comp.-Aided Design, pp. 13-16, San Jose CA, Nov. 2000.
  • F. Balasa, "Device-Level Placement for Analog Layout: An Opportunity for Non-Slicing Topological Representations,", Proc. Asia South Pacific Design Automation Conf., pp. 281-286, Yokohama, Japan, Jan.-Feb. 2001.
  • F. Balasa, S.C. Maruvada, "Using Non-Slicing Topological Representations for Analog Placement," IEICE Trans. On Fundamentals of Electronics, Communications and Computer Sciences (Special Section on VLSI Designa nd CAD Algorithms), Japan 2001.
  • IEEE Journal Article titled KOAN / ANAGRAM II: New Tools for Device-Level Analog Placement and Routing, by John M. Cohn, et al., 1991, pp. 330-342. (13 pages) Cited by 5 patents [ISI abstract]
  • Article titled An O-Tree Representation of Non-Slicing Floorplan and Its Applications, by Pei-Ning Guo, et al., 1999, pp. 268-273.
  • IEEE Journal Article titled "A New Algorithmm for Floorplan Design", by D.F. Wong and C.L. Liu, 1986, pp. 101-107.
  • IEEE Journal Article titled "Genetic Placement", by James P. Cohoon and William D. Paris, 1987, pp. 956-964. (9 pages) Cited by 2 patents
  • IEEE Journal Article titled "SALIM: A Layout Generation Tool for Analog ICs", by M. Kayal, et al., 1988, pp. 7.5.1-7.5.4.
  • IEEE Journal Article titled GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization, by Jurgen M. Kleinhans, et al., 1991, pp. 356-365. (10 pages) Cited by 20 patents [ISI abstract]
  • IEEE Journal Article titled "A Performance-Driven Placement Tool for Analog Integrated Circuits", by Koen lampaert, et al., 1995, pp. 773-780. (8 pages) [ISI abstract]
  • Article titled "Module Placement for Analog Layout Using the Sequence-Pair Representation", by Florin Balasa and Koen Lampaert, 1999, pp. 274-279.
  • IEEE Journal Article titled "Module Packing Based on the BSG-Structure and IC Layout", by Shigetoshi Nakatake, et al., 1998, pp. 519-530. (12 pages) [ISI abstract]
  • Society for Industrial and Applied Mathematics Article titled "Orthogonal Packings in Two Dimensions", by Brenda S. Baker, et al., 1980, pp. 846-855.
  • IEEE Journal Article titled "An Efficient Methodology for Symbolic Compaction of Analog IC's wiht Multiple Symmetry Constraints", by Eric Felt, et al., 1992, pp. 148-153.
  • IEEE Journal Article titled "Automation of IC Layout with Analog Constraints", by Enrico Malavasi, et al., 1996, pp. 923-942. (20 pages) [ISI abstract]
  • IEEE Journal Article titled "Quick Placement with Geometric Constraints", by Enrico Malavasi, et al., 1997, pp. 561-564.
  • IEEE Journal Article titled "STAT: A Schematic to Artwork Translator for Custom Analog Cells", by Stacy W. Mehranfar, 1990, pp. 30.2.1-30.2.3.
  • Article for IEEE Design Automoation Conference titled "Branch-and Bound Placement for Building Block Layout", by Hidetoshi Onodera, et al., 1991, pp. 433-439.
  • IEEE Journal Article titled "ILAC: An Automated Layout Tool for Analog CMOS Circuits", by Jef RijMenants, et al., 1989, pp. 417-423. (9 pages) Cited by 3 patents
  • IEEE Journal Article titled "Efficient and Effective Placement for Very Large Circuits", by Wern-Jieh Sun and Carl Sechen, 1995, pp. 349-359. (11 pages) Cited by 4 patents [ISI abstract]
  • IEEE Journal Article titled "An Analytical Approach to Floorplan Design and Optimization", by Suphachai Sutanthavibul, et al., 1991, pp. 761-769. (9 pages) Cited by 2 patents [ISI abstract]
  • IEEE Journal Article titled "An Analytical Approach to Floorplanning for Hierarchical Building Blocks Layout", by Chang-Sheng Ying and Joshua Sook-Leung Wong, 1989, pp. 403-412. (10 pages) Cited by 5 patents
  • IEEE Journal Article titled "VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair", by Hiroshi Murata, et al., 1996, pp. 1518-1524. (7 pages) Cited by 8 patents [ISI abstract]
  • IEEE Journal Article titled "The Timberwolf Placement and Routing Package", by Carl Sechen and Alberto Sangiovanni-Vincentelli, 1985, pp. 510-522. (13 pages) Cited by 5 patents
  • The Kluwer International Series in Engineering and Computer Science article titled "Analog Device-Level Layout Automation", by John M. Cohn, et al., pp. vi-vii and pp. 21-104.
  • Article titled "Virtual Symmetry Axes for the Layout of Analog IC's", by Enrico Malavasi, et al., pp. 1-10.
  • The Kluwer International Series in Engineering and Computer Science article titled "Analog Layout Generation for Performance and Manufacturability", by Koen Lampaert; et al., pp. 71-118.


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