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 Title: |
US6573769:
Phase-locked loop (PLL) with mixer for subtracting outer-band phase noise
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Zhang, Michael Y.; Palo Alto, CA
Choi, Tat; Saratoga, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2003-06-03
/ 2002-06-27
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| Application Number: |
US2002000064271
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| IPC Code: |
Advanced:
H03L 7/18;
H03L 7/089;
Core:
H03L 7/16;
more...
IPC-7:
H03L 7/06;
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| ECLA Code: |
H03L7/18;
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| U.S. Class: |
327/156;
327/147;
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| Field of Search: |
327/147,156,146,154,155,355,356,358,360,361,551,552,553
331/025,17
375/375,374,376
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| Priority Number: |
| 2002-06-27 |
US2002000064271 |
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| Abstract: |
A phase-locked loop (PLL) includes a final mixer on its output. The final mixer subtracts out a noise or error term from the PLL's output to reduce noise and jitter. A first mixer generates the error term by subtracting a feedback clock from the reference clock. This error term is near D.C. since the feedback and reference clocks are at the same frequency. When this error term is subtracted from the PLL output, a secondary maxima in the noise plot at the PLL's loop bandwidth is removed. A feedback counter receives the output of the voltage-controlled oscillator (VCO) before the final mixer. Outer-band noise created by the VCO is subtracted out by the final mixer, using the error term generated by the first mixer. The mixers reduce noise generated by the VCO or from other sources in the PLL.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Callahan, Timothy P.; Nguyen, Linh
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| INPADOC Legal Status: |
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| Family: |
None
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First Claim:
Show all 20 claims |
What is claimed is:
1. A noise-canceling phase-locked loop (PLL) comprising:
- a reference clock input that receives a reference clock with low phase noise;
- a phase comparator that receives the reference clock and a feedback clock and compares phases of the feedback and reference clocks;
- a loop filter that comprises a filter capacitor;
- a charge pump, responsive to a phase difference detected by the phase comparator, for charging and discharging the filter capacitor;
- a voltage-controlled oscillator (VCO) having an input that senses a filter voltage controlled by the filter capacitor, for generating a VCO clock that has a frequency that depends on the filter voltage;
- a feedback counter, receiving the VCO clock and generating the feedback clock;
- a first mixer, receiving the reference clock and receiving the feedback clock, for generating an error term; and
- a final mixer, receiving the VCO clock and the error term from the first mixer, for generating a final clock having reduced phase noise in comparison to the VCO clock,
- whereby noise is reduced by the final mixer.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 2 U.S. patent(s) that reference this one
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