 |
|
|
|
|
|
 Title: |
US6583656:
Differential clock driver with transmission-gate feedback to reduce voltage-crossing sensitivity to input skew
[ Derwent Title ]
|
| Country: |
US United States of America
|
| |
| Inventor: |
Liu, Wing Faat; San Jose, CA
|
| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
News, Profiles, Stocks and More about this company
|
| Published / Filed: |
2003-06-24
/ 2002-08-21
|
| Application Number: |
US2002000064831
|
| IPC Code: |
Advanced:
H03K 5/151;
Core:
more...
IPC-7:
H03K 5/12;
|
| ECLA Code: |
H03K5/151;
|
| U.S. Class: |
327/170;
327/108;
326/027;
|
| Field of Search: |
327/258,108,112,219,222,57,333,257,170
326/082,83,85,86,87,91,26-28
|
| Priority Number: |
| 2002-08-21 |
US2002000064831 |
|
| Abstract: |
A differential clock driver uses feedback to reduce timing skews between the true and complement differential outputs. Each of the differential outputs has a pull-up driver and a pull-down driver. Each pull-up or pull-down driver has an initial transistor and a final transistor in parallel to drive the output. A resistor separates gates of the initial and final transistors, causing a delay to enable the final transistor. A transmission gate provides feedback from the other output to the gate of the final transistor. When the other output is faster that the output being driven, the transmission gate transfers charge from the other output to the gate of the final transistor, causing it to speed up driving its output. This helps compensates for the timing skew between the outputs. Skews present on differential inputs can be compensated by the transmission gate feedback.
|
| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
|
| Primary / Asst. Examiners: |
Callahan, Timothy P.; Nguyen, Linh
|
| INPADOC Legal Status: |
Show legal status actions
|
| Family: |
None
|
First Claim:
Show all 21 claims |
What is claimed is:
1. A differential driver comprising:
- a true output and a complement output driven to opposite states when signaling information;
- a first true pull-up, coupled to the true output, for driving the true output high;
- a second true pull-up, coupled to the true output, for driving the true output high;
- a first feedback device, coupled between the complement output and a control gate of the second true pull-up, for accelerating driving of the true output high when the complement output is pulled low faster than the true output is pulled high;
- a first complement pull-up, coupled to the complement output, for driving the complement output high;
- a second complement pull-up, coupled to the complement output, for driving the complement output high; and
- a second feedback device, coupled between the true output and a control gate of the second complement pull-up, for accelerating driving of the complement output high when the true output is pulled low faster than the complement output is pulled high;
- a first true pull-down, coupled to the true output, for driving the true output low;
- a second true pull-down, coupled to the true output, for driving the true output low;
- a third feedback device, coupled between the complement output and a control gate of the second true pull-down, for accelerating driving of the true output low when the complement output is pulled high faster than the true output is pulled low;
- a first complement pull-down, coupled to the complement output, for driving the complement output low;
- a second complement pull-down, coupled to the complement output, for driving the complement output low; and
- a fourth feedback device, coupled between the true output and a control gate of the second complement pull-down, for accelerating driving of the complement output low when the true output is pulled high faster than the complement output is pulled low,
- whereby feedback reduces cross-over skew of the true and complement outputs.
|
| Background / Summary: |
Show background / summary
|
| Drawing Descriptions: |
Show drawing descriptions
|
| Description: |
Show description
|
| Forward References: |
Show 5 U.S. patent(s) that reference this one
|
|
