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 Title: |
US6583659:
Reduced clock-skew in a multi-output clock driver by selective shorting together of clock pre-outputs
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Kwong, David; Fremont, CA
Lin, Kwong Shing; Sunnyvale, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2003-06-24
/ 2002-02-08
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| Application Number: |
US2002000683744
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| IPC Code: |
Advanced:
G06F 1/10;
Core:
more...
IPC-7:
G06F 1/04;
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| ECLA Code: |
G06F1/10;
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| U.S. Class: |
Current:
327/295;
326/086;
327/112;
327/415;
365/233.14;
Original:
327/295;
327/112;
327/415;
326/086;
365/233;
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| Field of Search: |
327/291,293,295-297,403,404,395,108,109,112,387,415
375/356
365/233,233.5
326/082,83,85,21-28,86-87,93,95
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| Priority Number: |
| 2002-02-08 |
US2002000683744 |
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| Abstract: |
A clock driver chip has several banks of clock outputs driven by a single clock reference. Each clock output is driven by large pull-up and pull-down transistors, which have gates driven by pre-driver lines generated by a pre-driver circuit. Individual clock outputs, or a bank of outputs, are enabled by enable signals. A shorting switch is activated when enables for a pair of clock outputs are in a same state. The shorting switch has two transmission gates. One transmission gate shorts the pre-driver lines to the large p-channel transistors of the pair of outputs, while the other transmission gate shorts the pre-driver lines to the large n-channel transistors of the pair of outputs. Pre-driver lines to the pull-up transistors within a bank driven by the same enable can be hardwired together, as can the pre-driver lines to the pull-down transistors. Shorting switches can short banks together to reduce output skew.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Nguyen, Minh;
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 20 claims |
What is claimed is:
1. A parallel clock driver comprising:
- a reference clock;
- a plurality of pre-driver circuits, responsive to the reference clock, each pre-driver circuit outputting a pull-up pre-driver line and a pull-down pre-driver line and receiving an enable signal having an enabling state that enables the pre-driver circuit to drive high and low the pull-up and pull-down pre-driver lines in response to the reference clock;
- a plurality of output buffers, each having a pull-up transistor with a gate driven by the corresponding pull-up pre-driver line, and a pull-down transistor with a gate driven by the corresponding pull-down pre-driver line, each driving a clock output with the pull-up transistor and the pull-down transistor; and
- a plurality of shorting switches, each shorting switch receiving a pair of the enable signals for a pair of the pre-driver circuits, the shorting switch connecting together the pull-up pre-driver lines generated by the pair of pre-driver circuits when the pair of enable signals are both in the enabling state,
- whereby the pull-up pre-driver lines are connected together by the shorting switch when the pair of the pre-driver circuits are both enabled.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 4 U.S. patent(s) that reference this one
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