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 Title: |
US6628175:
Voltage-controlled crystal oscillator (VCXO) using MOS varactors coupled to an adjustable frequency-tuning voltage
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Guo, Zhangqi; San Jose, CA
Hattori, Hide; Palo Alto, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2003-09-30
/ 2002-03-27
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| Application Number: |
US2002000063167
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| IPC Code: |
Advanced:
H03B 5/36;
H03K 3/03;
H03B 1/00;
H03K 3/354;
Core:
H03K 3/00;
more...
IPC-7:
H03B 5/32;
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| ECLA Code: |
H03B5/36C; H03K3/03B;
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| U.S. Class: |
331/158;
331/109;
331/116.FE;
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| Field of Search: |
331/177 R,181,177 V,158,160,108 R,116 FE,109
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| Priority Number: |
| 2002-03-27 |
US2002000063167 |
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| Abstract: |
A voltage-controlled crystal oscillator (VCXO) has variable load capacitors on the crystal nodes. The variable load capacitors are p-channel or n-channel transistors with their source and drain nodes connected to a crystal node. The gates are driven by an input voltage that is generated from a full-swing control voltage by a voltage conversion circuit. The input voltage has a half-swing of only half of the power-supply voltage, or VDD/2. The input voltage driving n-channel capacitors swings from VDD to VDD/2, which is just above the source voltage of VDD/2 on the crystal node and ensures that the n-channel capacitors remain on for most of the range. A series of resistors can divide the input voltage into a series of differing voltages that drive gates of multiple n-channel capacitors that have their source/drains connected in parallel to the crystal node. Capacitance increases as an n-channel capacitor channel turns on.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Nguyen, Minh;
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 16 claims |
What is claimed is:
1. A Voltage-controlled crystal oscillator (VCXO) comprising:
- a crystal, coupled between a first node and a second, that oscillates at an oscillation frequency when connected to a gain inverter;
- the gain inverter having an input driven by the first node, for driving the second node to induce oscillation by the crystal;
- a feedback resistor coupled between the first and second nodes;
- a first metal-oxide-semiconductor (MOS) capacitor, having a source/drain coupled to the first node, and a gate coupled to a first gate node, the first MOS capacitor having a capacitance that varies with a first input voltage of the first gate node; and
- a second MOS capacitor, having a source/drain coupled to the second node, and a gate coupled to a second gate node, the second MOS capacitor having a capacitance that varies with a second input voltage of the second gate node;
- wherein the first and second gate nodes are connected together and driven by an input voltage, wherein the oscillation frequency and capacitances of the first and
- a controlled input for a control voltage that can vary from a ground to a power-supply VDD voltage, the control voltage causing the oscillation frequency increases when the control voltage rises, but causing the oscillation frequency decreases when the control voltage falls;
- voltage conversion circuit means, receiving the control voltage, for generating the input voltage, and for limiting the input voltage to only half of a range of the control voltage;
- wherein the first and second MOS capacitors are n-channel capacitors;
- wherein the input voltage falls from VDD/2 when the control voltage rises from ground to VDD;
- wherein the intermediate voltage of the first and second nodes is VDD 2;
- wherein the voltage conversion circuit means comprises:
- op amp means, having an inverting and a non-inverting input, for generating the input voltage on an output;
- an input resistor between the control voltage input and the inverting input to the op amp means;
- voltage divider means for generating a reference voltage applied to the non-inverting input of the op amp means;
- a feedback resistor between the output and the inverting input of the op amp means;
- an output resistor between the output of the op amp means and the first gate node,
- whereby the first and second MOS capacitors are driven by the input voltage that is at or above a source/drain voltage to bias the first and second MOS transistors in an on region of operation for most of a range of the control voltage and whereby a full-swing control voltage is converted to a half-swing input voltage to gates of the first and second MOS capacitors and whereby variations in the input voltage vary the oscillation frequency by adjusting capacitances of the first and second MOS capacitors and whereby changes to the control voltages are inverted and halved by the voltage conversion circuit means to generate the input voltage.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
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| Forward references (3)
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Backward references (20)
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Patent |
Pub.Date |
Inventor |
Assignee |
Title |
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