 |
|
|
|
|
|
 Title: |
US6665776:
Apparatus and method for speculative prefetching after data cache misses
[ Derwent Title ]
|
| Country: |
US United States of America
|
| |
| Inventor: |
Jouppi, Norman Paul; Palo Alto, CA
Farkas, Keith Istvan; San Carlos, CA
|
| Assignee: |
Hewlett-Packard Development Company L.P., Houston, TX
other patents from HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (815532) (approx. 1,981)
News, Profiles, Stocks and More about this company
|
| Published / Filed: |
2003-12-16
/ 2001-01-04
|
| Application Number: |
US2001000755719
|
| IPC Code: |
Advanced:
G06F 9/30;
G06F 9/38;
G06F 12/08;
Core:
more...
IPC-7:
G06F 12/00;
|
| ECLA Code: |
G06F9/30R4S; G06F9/38F; G06F9/38H2; G06F12/08B8; G06F9/38D2; G06F9/38D4;
|
| U.S. Class: |
Current:
711/137;
711/E12.057;
712/207;
712/E09.027;
712/E09.047;
712/E09.048;
712/E09.055;
712/E09.061;
Original:
711/137;
712/207;
|
| Field of Search: |
711/137,119,120,124,128,140
712/207
|
| Priority Number: |
| 2001-01-04 |
US2001000755719 |
|
| Abstract: |
A microprocessor is configured to continue execution in a special Speculative Prefetching After Data Cache Miss (SPAM) mode after a data cache miss is encountered. The microprocessor includes additional registers and program counter, and optionally additional cache memory for use during the special SPAM mode. By continuing execution during the SPAM mode, multiple outstanding and overlapping cache fill requests may be issued, thus improving performance of the microprocessor.
|
| Primary / Asst. Examiners: |
McLean-Mayo, Kimberly;
|
| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
|
| Family: |
Show 4 known family members
|
First Claim:
Show all 14 claims |
What is claimed is:
1. A processor having a normal mode and a speculative prefetching mode, the processor operable in the speculative prefetching mode after a data cache miss, comprising:
- a first data cache for storing data when the processor operates in the normal mode;
- a second data cache for storing data in response to a store instruction when the processor operates in the speculative prefetching mode, comprising:
- an entry for storing data; and
- a trash bit associated with the entry, wherein the trash bit indicates whether the entry contains arbitrary data; and
- a control logic for setting the trash bit of the second data cache when a source operand for the store instruction depends on the data cache miss.
|
| Background / Summary: |
Show background / summary
|
| Drawing Descriptions: |
Show drawing descriptions
|
| Description: |
Show description
|
| Forward References: |
Show 6 U.S. patent(s) that reference this one
|
|
|
|
|
|
|
| Foreign References: |
None
|
| Other Abstract Info: |
DERABS C2002-626778
|
| Other References: |
Jegou et al., ACM--Speculative Prefetching, 1993, pp. 59-62.*
Hennessy and Patterson, Computer Organization and Design, Dec. 1998, Morgan Kaufman Publishers, 2nd edition, p. 541.*
Mano, Computer Engineering: Hardware Design, Dec. 1988, Prentice-Hall, pp., 152-153 and 187-193.*
Handy, The Cache Memory Book, 12, 1998, Academic Press, 2nd edition, p. 51 and 54.
|
| Continuity Data: |
| Application Number | Filed | Notes |
|---|
|
|
US2001000755719 | 2001-01-04 | is a
related to the prior publication |
| |
US20040088491A1 issued 2004-05-06 Apparatus and method for speculative prefetching after data cache misses
|
|
|
|
US2003000693303 | 2003-10-24 | is a
continuation of |
|
>US2001000755719<
| 2001-01-04 |
(granted)
|
| |
US6665776 issued 2003-12-16 Apparatus and method for speculative prefetching after data cache misses
|
|
|
|
US2003000693303 | | is a
continuation of |
|
>US2001000755719<
| 2001-01-04 |
|
| |
US6665776 issued 2003-12-16 Apparatus and method for speculative prefetching after data cache misses
|
|
|
|
 Nominate this for the Gallery...
|
|
