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 Title: |
US6686763:
Near-zero propagation-delay active-terminator using transmission gate
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Yen, Yao Tung; Cupertino, CA
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| Assignee: |
Pericam Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2004-02-03
/ 2002-05-16
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| Application Number: |
US2002000063827
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| IPC Code: |
Advanced:
H03K 17/042;
H03K 17/16;
H03K 19/00;
H03K 19/017;
Core:
more...
IPC-7:
H03K 19/003;
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| ECLA Code: |
H03K17/042B; H03K17/16B4B2; H03K19/00P4; H03K19/017B2;
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| U.S. Class: |
326/030;
326/031;
326/026;
326/027;
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| Field of Search: |
326/026,27,30-34,82,83
327/108-112
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| Priority Number: |
| 2002-05-16 |
US2002000063827 |
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| Abstract: |
A transmission line is terminated by a buffer. The buffer isolates a load from the transmission line using a transmission gate. The transmission gate is turned off and does not conduct most of the time, but turns on when a transition is detected on the transmission line, allowing the transmission line to directly drive the load for a short time. Once the load is switched beyond a logic threshold voltage, the transmission gate is again turned off and a latch or latching transistors driven by the transmission line continue to drive the isolated load to power or ground voltages. Driver transistors are also enabled when the transmission gate is turned on, driving either the output (load) node or the input (transmission line) node with the new data. Feedback from the output node disables the transmission gate and driver transistors once the output has been driven past the logic threshold.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Tran, Anh;
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 22 claims |
What is claimed is:
1. An active terminating buffer for a transmission line comprising:
- an input node from a far end of a transmission line that receives a signal sent from a driver at another end of the transmission line;
- an output node coupled to a load to be driven by the transmission line;
- a pass transistor coupled to conduct current between the input and output nodes when the pass transistor is enabled by a gate signal, but for isolating the output node from the input node when the pass transistor is disabled by the gate signal;
- control logic, receiving the output node and the input node as inputs, for activating the gate signal to enable the pass transistor to connect the transmission line to the load when the input node is in an opposite logical state from the output node, but for de-activating the gate signal to disable the pass transistor and isolate the load from the transmission line when the output node is in a same logical state as the input node;
- latch means, on the output node, for continuing to drive the output node when the gate signal disables the pass transistor to isolate the load from the transmission line; and
- drive means, responsive to the gate signal and activated when the pass transistor is enabled, but de-activated when the pass transistor isolates the load from the transmission line, for driving the load to a same logical state as a logical state of the input node,
- whereby the pass transistor connects the transmission line to the load when the gate signal is activated, but isolates the transmission line from the load when the gate signal is de-activated.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 3 U.S. patent(s) that reference this one
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