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 Title: |
US6693480:
Voltage booster with increased voltage boost using two pumping capacitors
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Wong, Anthony Yap; Cupertino, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2004-02-17
/ 2003-03-27
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| Application Number: |
US2003000249282
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| IPC Code: |
Advanced:
H02M 3/07;
H03K 17/06;
Core:
H02M 3/04;
more...
IPC-7:
H03K 17/16;
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| ECLA Code: |
H02M3/07S; H03K17/06B;
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| U.S. Class: |
327/390;
327/536;
363/060;
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| Field of Search: |
827/108,112,389,390,306,536
363/059,60
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| Priority Number: |
| 2003-03-27 |
US2003000249282 |
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| Abstract: |
A voltage booster drives the gate of a bus-switch n-channel transistor to a theoretical maximum of triple the power-supply voltage Vcc. The gate node is first driven to Vcc. Then the back-side of a first capacitor is driven from ground to Vcc, coupling a first voltage boost to the gate node. After a Schmidt-trigger detects the back-side of the first capacitor near Vcc, the back-side of a second capacitor is driven from ground to Vcc. The front-side of the second capacitor is connected to the back-side of the first capacitor. A second voltage boost is coupled across the first and second capacitors to increase the voltage boost of the gate node to near triple Vcc rather than just double Vcc.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Nguyen, Long;
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| INPADOC Legal Status: |
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| Family: |
None
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First Claim:
Show all 20 claims |
What is claimed is:
1. A double-boost voltage booster comprising:
- a buffer for buffering an input signal to generate a buffered input signal;
- a charge pump for generating a pumped voltage above a power-supply voltage;
- a boosted node driven from ground to a boosted voltage above the power-supply voltage;
- a pull-down n-channel transistor, coupled to drive the boosted node to ground in response to the buffered input signal;
- a pull-up p-channel transistor, having a gate controlled by the buffered input signal, for coupling the boosted node to a keeper node;
- a keeper p-channel transistor, coupled to supply a keeper current to the keeper node from the charge pump, the keeper p-channel transistor having a keeper gate;
- a control node, initially driven low in response to the buffered input signal;
- a first p-channel transistor, having a drain coupled to the boosted node and a source coupled to a power source providing the power-supply voltage, for conducting current from the power source to the boosted node in response to the control node applied to a gate of the first p-channel transistor;
- a second p-channel transistor, having a drain coupled to the control node and a source coupled to the pumped voltage from the charge pump, for conducting current from the pumped voltage to the control node, the second p-channel transistor having a gate controlled by a delayed node;
- a first delay line, having a first inverter with an input connected to the boosted node, for delaying a rising transition of the boosted node to drive the delayed node to control the second p-channel transistor and for driving a first back-side node;
- a first capacitor, coupled between the first back-side node and the boosted node, for coupling a first voltage swing output by the first delay line to the boosted node;
- a second delay line, having a second inverter with an input connected to the first back-side node, for delaying a rising transition of the first back-side node to drive a second back-side node; and
- a second capacitor, coupled between the first back-side node and the second back-side node, for coupling a second voltage swing output by the second delay line to the first back-side node,
- whereby the first voltage swing is coupled to the boosted node through the first capacitor and the second voltage swing is coupled to the boosted node through the first and second capacitors.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 4 U.S. patent(s) that reference this one
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