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Title: US6693987: Digital-to-analog DAC-driven phase-locked loop PLL with slave PLL's driving DAC reference voltages
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Country: US United States of America

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9 pages

 
Inventor: Hattori, Hide; Palo Alto, CA

Assignee: Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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Published / Filed: 2004-02-17 / 2000-10-05

Application Number: US2000000679682
IPC Code: Advanced: H03L 7/089; H03L 7/23;
Core: H03L 7/16; more...
IPC-7: H03D 3/24;

ECLA Code: H03L7/089C; H03L7/23;

U.S. Class: 375/376; 327/156;

Field of Search: 375/215,294,327,373,374,375,376 327/055,58,68,90,3,5,16,37,40,147,156,157 329/306,307,359,358,360 331/025,2,11

Priority Number:
2000-10-05  US2000000679682

Abstract:     A clock generator uses two PLL loops and a digital-to-analog converter (DAC) to generate a variable output frequency from a single fixed-frequency reference clock. Each PLL loop receives the reference clock and phase-compares it with a feedback clock. The feedback clock in one loop is slightly faster in frequency than the feedback clock in the second loop. The input voltages to voltage-controlled oscillators (VCOs) in the two loops thus vary slightly. A DAC is connected between the two VCO inputs. The DAC's two reference-voltage inputs are connected to these VCO inputs. The DAC's output voltage is selected from within the voltage range between the two VCO voltages by a digital code-word input to the DAC. The DAC's output voltage is input to a final VCO that generates the variable output frequency. The output frequency is varied by selecting the digital code-word input to the DAC.

Attorney, Agent or Firm: Auvinen, Stuart T. ;

Primary / Asst. Examiners: Bayard, Emmanuel;

INPADOC Legal Status: Show legal status actions

Family: None
First Claim:
Show all 20 claims		 I claim:     1. A dual-loop digitally-tuned clock generator comprising:
  • a reference-clock input, having a reference frequency;
  • a first phase-locked loop, receiving the reference-clock input, for generating a first feedback clock having a first feedback frequency, the first phase-locked loop phase comparing the reference-clock input to the first feedback clock, the first phase-locked loop charging and discharging a first capacitance in response to phase comparison to adjust a first voltage;
  • a second phase-locked loop, receiving the reference-clock input, for generating a second feedback clock having a second feedback frequency, the second phase-locked loop phase comparing the reference-clock input to the second feedback clock, the second phase-locked loop charging and discharging a second capacitance in response to phase comparison to adjust a second voltage;
  • wherein the second voltage differs from the first voltage;
  • a digital-to-analog converter (DAC) coupled between the first voltage and the second voltage, the DAC for generating a selectable voltage, wherein the selectable voltage is a voltage between the first voltage and the second voltage, the selectable voltage being selectable by a digital select input to the DAC; and
  • an output-clock generator, coupled to the DAC by selectable voltage, for generating an output clock having an output frequency, the output frequency determined by the selectable voltage,
  • whereby the output frequency is determined by the selectable voltage of the DAC coupled between the first and second phase-locked loops.
    •


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Forward References: Show 5 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (5)   |   Backward references (22)   |   Citation Link

Buy
PDF		 Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 7pp US4516084  1985-05 Crowley  RCA Corporation Frequency synthesizer using an arithmetic frequency synthesizer and plural phase locked loops
Buy PDF- 27pp US4724476  1988-02 Nakagawa et al.  Matsushita Electric Industrial Co., Ltd. Chrominance signal processing apparatus
Buy PDF- 11pp US5231475  1993-07 Ritter et al.  Videotek, Inc. Method and apparatus for generating video signal representing controllable color matte
Buy PDF- 24pp US5262957  1993-11 Hearn  Global Communications, Inc. Inexpensive portable RF spectrum analyzer with calibration features
Buy PDF- 12pp US5329251  1994-07 Llewellyn  National Semiconductor Corporation Multiple biasing phase-lock-loops controlling center frequency of phase-lock-loop clock recovery circuit
Buy PDF- 7pp US5422604  1995-06 Jokura  NEC Corporation Local oscillation frequency synthesizer for vibration suppression in the vicinity of a frequency converging value
Buy PDF- 8pp US5479073  1995-12 Mamiya et al.  International Business Machines Corporation Dot clock generator for liquid crystal display device
Buy PDF- 10pp US5566204  1996-10 Kardontchik et al.  Raytheon Company Fast acquisition clock recovery system
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Buy PDF- 10pp US5610558  1997-03 Mittel et al.  Motorola, Inc. Controlled tracking of oscillators in a circuit with multiple frequency sensitive elements
Buy PDF- 10pp US5659586  1997-08 Chun  Samsung Electronics Co., Ltd. Digital timing recovery circuit including a loop filter having a varying band width
Buy PDF- 12pp US5809397  1998-09 Harthcock et al.  Motorola, Inc. Method and apparatus for system synchronization in a messaging system
Buy PDF- 10pp US5838205  1998-11 Ferraiolo et al.  International Business Machines Corporation Variable-speed phase-locked loop system with on-the-fly switching and method therefor
Buy PDF- 9pp US5881111  1999-03 Anzai  NEC Corporation Frequency sweep circuit
Buy PDF- 12pp US5943382  1999-08 Li et al.  NeoMagic Corp. Dual-loop spread-spectrum clock generator with master PLL and slave voltage-modulation-locked loop
Buy PDF- 14pp US5950115  1999-09 Momtaz et al.  Adaptec, Inc. GHz transceiver phase lock loop having autofrequency lock correction
Buy PDF- 10pp US6064869  2000-05 Davis et al.  Motorola, Inc. Suppression of noise between phase lock loops in a selective call receiver and method therefor
Buy PDF- 18pp US6097560  2000-08 Tanaka et al.  Canon Kabushiki Kaisha Reproducing apparatus having clock generator controlled by detected phase-difference and tendency of phase-difference
Buy PDF- 12pp US6115586  2000-09 Bezzam et al.  Integrated Circuit Systems, Inc. Multiple loop radio frequency synthesizer
Buy PDF- 8pp US6188258  2001-02 Nakatani  Mitsubishi Electric System LSI Design Corporation Clock generating circuitry
Buy PDF- 10pp US6204732  2001-03 Rapoport et al.  ECI Telecom Ltd Apparatus for clock signal distribution, with transparent switching capability between two clock distribution units
Buy PDF- 8pp US6570948  2003-05 Marshall  Koninklijke Phillips Electronics N.V. Phase locked loop frequency generating circuit and a receiver using the circuit
       
Foreign References: None

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