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 Title: |
US6724224:
Bus relay and voltage shifter without direction control input
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Li, Xianxin; Milpitas, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2004-04-20
/ 2003-04-07
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| Application Number: |
US2003000249413
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| IPC Code: |
Advanced:
H03K 19/0185;
H04L 5/16;
H03K 5/00;
Core:
more...
IPC-7:
H03K 19/00;
H03K 19/0175;
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| ECLA Code: |
H03K19/0185B4; H03K19/0185R; H04L5/16;
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| U.S. Class: |
326/082;
326/056;
326/093;
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| Field of Search: |
326/082-83,56-58,93
327/108,109,141,161
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| Priority Number: |
| 2003-04-07 |
US2003000249413 |
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| Abstract: |
A bi-directional bus-interface chip has no direction-control input. A forward buffer and a reverse buffer are both normally disabled in the high-impedance state. When a transition occurs on one input bus, a driver transistor in the forward or reverse buffer is activated to pass the transition through the bus-interface chip. After a delay, the driver transistor is disabled. An optional bus-hold circuit maintains voltage levels on buses when driver transistors are disabled. The delay can be selectable by shorting delay resistors in the delay circuit. The high-level voltages on the two busses may differ. The bus-interface chip converts one voltage domain to another and can re-generate weak signals. A pre-buffer may be added to gradually step up the voltage level when differences in voltage domains are large.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Cho, James H;
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 20 claims |
What is claimed is:
1. A bus-interface chip without a direction-control input comprising:
- a plurality of bit slices between bits of a first bus and corresponding bits of a second bus, each bit slice comprising:
- a forward buffer having an input coupled to a first bus line that is a bit of the first bus and an output for driving a second bus line that is a bit of the second bus;
- a first delay, coupled to the first bus line, for generating a first delayed signal after a delay from a transition on the first bus line;
- the forward buffer being enabled to drive the second bus line in response to the transition on the first bus line, the forward buffer being disabled from driving the second bus line in response to the first delayed signal;
- a reverse buffer having an input coupled to the second bus line and an output for driving the first bus line; and
- a second delay, coupled to the second bus line, for generating a second delayed signal after a delay from a transition on the second bus line;
- the reverse buffer being enabled to drive the first bus line in response to the transition on the second bus line, the reverse buffer being disabled from driving the first bus line in response to the second delayed signal,
- whereby the forward buffer and the reverse buffer are enabled and disabled without using a direction-control input to the bus-interface chip.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 5 U.S. patent(s) that reference this one
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