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 Title: |
US6724592:
Substrate-triggering of ESD-protection device
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Tong, Paul C. F.; San Jose, CA
Ker, Ming-Dou; Hsinchu, Taiwan
Xu, Ping Ping; San Jose, CA
Lin, Kwong Shing; Sunnyvale, CA
Tam, Anna; Cupertino, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2004-04-20
/ 2002-12-11
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| Application Number: |
US2002000248018
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| IPC Code: |
Advanced:
H01L 27/02;
H02H 9/00;
Core:
more...
IPC-7:
H02H 9/00;
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| ECLA Code: |
H01L27/02B4F6;
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| U.S. Class: |
361/056;
361/111;
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| Field of Search: |
361/056,111,91.1,91.3,86,119
257/355
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| Priority Number: |
| 2002-12-11 |
US2002000248018 |
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| Abstract: |
Pin-to-pin electro-static-discharge (ESD) protection is provided for a bus-switch transistor that is connected to I/O pins at its source and drain. A p-type substrate is normally pumped below ground by a substrate bias generator when power is applied. However, during a pin-to-pin ESD test, power and ground are floating. A gate node is pulled high through a coupling capacitor by the ESD pulse. The gate node turns on a shunting transistor to couple the ESD pulse to the floating ground bus. The gate node also turns on a shorting transistor that connects the floating ground bus to the floating substrate. A resistor drains the coupling capacitor to the substrate, rather than to ground. Current is injected into the substrate by the resistor. The snapback voltage is lowered by substrate-triggering.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Jackson, Stephen W.; Demakis, James A
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| INPADOC Legal Status: |
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| Family: |
None
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First Claim:
Show all 20 claims |
What is claimed is:
1. A pin-to-pin electro-static-discharge (ESD) protection device comprising:
- an input node that receives an ESD pulse;
- an internal ground bus;
- a substrate node;
- a coupling capacitor between the input node and a trigger node;
- a shunting transistor having a gate connected to the trigger node, for conducting current between the input node and the internal ground bus during an ESD event;
- a shorting transistor having a gate connected to the trigger node, for conducting current between the internal ground bus and the substrate node during the ESD event; and
- an injecting resistor, coupled between the trigger node and the substrate node, for injecting current into the substrate node during the ESD event, whereby portions of the ESD pulse are conducted to the internal ground bus and to the substrate node.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 8 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other Abstract Info: |
DERABS C2004-386909
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| Other References: |
Chen et al, "Investigation of the Gate-Driven Effect and Substrate-Triggered Effect on ESD Robustness of CMOS Devices", IEEE Trans. Device & Materials Reliab., Vol 1, No. 4, Dec. 2002, pp. 190-203.
Ker et al., "ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process", IEEE Proc. Int'l Sym. Quality Electronic Design (ISQED'02), 4/02, p. 1-6.
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