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 Title: |
US6762634:
Dual-loop PLL with DAC offset for frequency shift while maintaining input tracking
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Hattori, Hide; Palo Alto, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2004-07-13
/ 2003-08-13
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| Application Number: |
US2003000604730
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| IPC Code: |
Advanced:
H03L 7/07;
H03L 7/10;
Core:
H03L 7/08;
more...
IPC-7:
H03L 7/06;
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| ECLA Code: |
H03L7/07; H03L7/10;
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| U.S. Class: |
327/159;
331/049;
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| Field of Search: |
327/145-150,156-159
331/011,46,49
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| Priority Number: |
| 2003-08-13 |
US2003000604730 |
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| Abstract: |
A phase-locked loop (PLL) keeps tracking a reference clock when a frequency offset is introduced. The PLL has primary and secondary PLL loops. A digital-to-analog converter (DAC) generates a current that is passed through an offset resistor to generate an offset voltage. An op amp is inserted in the primary loop between a filter capacitor and a voltage-controlled oscillator (VCO). The offset resistor is coupled between the inverting input of the op amp and the op amp's output. When the DAC offset occurs, the voltage to the VCO and the frequency of the primary loop change and the primary loop loses tracking of the reference clock. The secondary loop keeps tracking the reference clock during the DAC offset while the primary loop is open. Then the output clock of the secondary loop is applied as the feedback clock to the phase comparator of the primary loop.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Callahan, Timothy P.; Cox, Cassandra
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| INPADOC Legal Status: |
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| Family: |
None
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First Claim:
Show all 17 claims |
What is claimed is:
1. An offsetting phase-locked loop (PLL) comprising:
- a primary phase comparator, receiving a reference clock and a primary feedback clock;
- a primary filter capacitor for generating a primary filter voltage;
- a primary charge pump, activated by phase differences detected by the primary phase comparator, for charging and discharging the primary filter capacitor;
- a primary voltage-controlled oscillator (VCO) for generating a primary output clock having an output frequency that is a function of a primary VCO input voltage of a primary VCO input;
- an op amp having a first input receiving the primary filter voltage, and an output driving the primary VCO input;
- an offset resistor, coupled between the primary VCO input and a second input to the op amp;
- a digital-to-analog converter (DAC) receiving a digital value, for generating a DAC current as a function of the digital value, the DAC current being driven through the offset resistor;
- a secondary phase comparator, receiving the reference clock and a secondary feedback clock;
- a secondary filter capacitor for generating a secondary filter voltage;
- a secondary charge pump, activated by phase differences detected by the secondary phase comparator, for charging and discharging the secondary filter capacitor;
- a secondary voltage-controlled oscillator (VCO) for generating a secondary output clock having an output frequency that is a function of the secondary filter voltage; and
- a coupling switch, between the secondary VCO and the primary phase comparator, for coupling the secondary output clock to the primary feedback clock after the DAC generates the DAC current,
- whereby the DAC generates the DAC current to offset a voltage of the primary VCO input.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 3 U.S. patent(s) that reference this one
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