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Title: US6820142: Token based DMA
[ Derwent Title ]


Country: US United States of America

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12 pages

 
Inventor: Hofstee, Harm Peter; Austin, TX
Nair, Ravi; Briarcliff Manor, NY
Wellman, John-David; Peekskill, NY

Assignee: International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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Published / Filed: 2004-11-16 / 2000-12-14

Application Number: US2000000736356

IPC Code: Advanced: G06F 13/28;
Core: G06F 13/20;
IPC-7: G06F 13/28;

ECLA Code: G06F13/28;

U.S. Class: 710/025; 710/023; 710/028;

Field of Search: 710/023,28,22 711/005,147-152,163 370/230,395.42,369,375-379 345/560 709/230

Priority Number:
2000-12-14  US2000000736356

Abstract:     A method and system for accessing a shared memory in a deterministic schedule. In one embodiment, a system comprises a plurality of processing elements and a system I/O controller where each processing element and system I/O controller comprises a DMA controller. The system further comprises a shared memory coupled to each of the plurality of processing elements where the shared memory comprises a master controller. The master controller may then issue tokens to DMA controllers to grant the right for the associated processing elements and system I/O controller to access the shared memory at deterministic points in time. Each token issued by the master controller grants access to the shared memory for a particular duration of time at a unique deterministic point in time. A processing element or system I/O controller may access the shared memory upon the associated DMA controller relinquishing to the master controller the token that grants the right to access the shared memory at that particular time. The master controller may then reissue the relinquished token back to the DMA controller associated with the processing element or system I/O controller that accessed the shared memory if at a future designated time, e.g., 128 ns from the completion of the access to the shared memory, there does not exist a higher prioritized request, e.g., refresh the shared memory, to access the shared memory at that future designated time. The reissued token grants the right to access the shared memory at the future designated time.

Attorney, Agent or Firm: Voigt, Jr., Robert A.Winstead Sechrest & Minick P.C. ; Salys, Casimer K. ;

Primary / Asst. Examiners: Gaffin, Jeffrey; Schneider, Joshua D

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Parent Case:

CROSS REFERENCE TO RELATED APPLICATIONS
    The present invention is related to the following U.S. patent applications which are incorporated herein by reference:
    Ser. No. 09/736,452 entitled "Reduction of Interrupts in Remote Procedure Calls" filed Dec. 14, 2000.
    Ser. No. 09/736,585 entitled "Symmetric Multi-Processing System" filed Dec. 14, 2000.

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First Claim:
Show all 20 claims
What is claimed is:     1. A system comprising:
  • a plurality of processing elements, wherein each processing element of said plurality of processing elements comprises a direct memory access controller, and
  • a shared memory coupled to said plurality of processing elements, wherein said shared memory comprises a master controller, wherein said master controller is operable for issuing tokens to direct memory access controllers for accessing said shared memory at deterministic points in time.


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Forward References: Show 6 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (6)   |   Backward references (9)   |   Citation Link

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Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 14pp US4658247  1987-04 Gharachorloo  Cornell Research Foundation, Inc. Pipelined, line buffered real-time color graphics display system
Buy PDF- 7pp US5068849  1991-11 Tanaka  Mitsubishi Denki Kabushiki Kaisha Cyclic data transmission method
Buy PDF- 8pp US5734926  1998-03 Feeley et al.  Advanced Hardware Architectures Direct memory access controller in an integrated circuit
Buy PDF- 26pp US6011798  2000-01 McAlpine  Intel Corporation Adaptive transmit rate control scheduler
Buy PDF- 39pp US6026443  2000-02 Oskouy et al.  Sun Microsystems, Inc. Multi-virtual DMA channels, multi-bandwidth groups, host based cellification and reassembly, and asynchronous transfer mode network interface
Buy PDF- 9pp US6029225  2000-02 McGehearty et al.  Hewlett-Packard Company Cache bank conflict avoidance and cache collision avoidance
Buy PDF- 9pp US6070194  2000-05 Yu et al.  Advanced Micro Devices, Inc. Using an index and count mechanism to coordinate access to a shared resource by interactive devices
Buy PDF- 14pp US6275877  2001-08 Duda   Memory access controller
Buy PDF- 39pp US6393512  2002-05 Chen et al.  ATI International SRL Circuit and method for detecting bank conflicts in accessing adjacent banks
       
Foreign References: None

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