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 Title: |
US6839828:
SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Gschwind, Michael Karl; Mohegan Lake, NY, United States of America
Hofstee, Harm Peter; Austin, TX, United States of America
Hopkins, Martin Edward; Chappaqua, NY, United States of America
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| Assignee: |
International Business Machines Corporation, Armonk, NY, United States of America
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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| Published / Filed: |
2005-01-04
/ 2001-08-14
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| Application Number: |
US2001000929805
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| IPC Code: |
Advanced:
G06F 9/00;
G06F 9/30;
G06F 9/312;
G06F 9/38;
G06F 15/80;
Core:
G06F 15/76;
more...
IPC-7:
G06F 15/80;
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| ECLA Code: |
G06F9/30R4; G06F9/30R4S; G06F9/312; G06F9/38T;
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| U.S. Class: |
Current:
712/020;
712/003;
712/022;
712/E09.025;
712/E09.027;
712/E09.033;
712/E09.071;
713/324;
Original:
712/020;
712/003;
712/022;
713/324;
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| Field of Search: |
712/003,20,22,32
713/324
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| Priority Number: |
| 2001-08-14 |
US2001000929805 |
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| Abstract: |
There is provided a processor designed to operate in a plurality of modes for processing vector and scalar instructions. Register files are each for storing scalar and vector data and address information. A parallel vector unit, coupled to the register files, includes functional units configurable to operate in a vector operation mode and a scalar operation mode. The vector unit includes an apparatus for tightly coupling the functional units to perform an operation specified by a current instruction. Under a vector operation mode, the vector unit performs, in parallel, a single vector operation on a plurality of data elements. The operations performed on the plurality of data elements are each performed by a different functional unit of the vector unit. Under a scalar operation mode, the vector unit performs a scalar operation on a data element received from the register files in a functional unit within the vector unit.
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| Attorney, Agent or Firm: |
Keusey, Tutunjian & Bitetto, P.C. ;
Percello, Louis J. ;
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| Primary / Asst. Examiners: |
Kim, Kenneth S.;
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| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
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| Family: |
Show 2 known family members
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First Claim:
Show all 21 claims |
1. A processor designed to operate in a plurality of modes for processing vector and scalar instructions, where a vector instruction identifies a single operation to be performed on a plurality of data elements, and a scalar instruction identifies a single operation to be performed on a single data element, comprising: one or more register, files, each for storing data directly usable as scalar data vector data and address information; a parallel vector unit coupled to receive data from the one or more register files and comprising a plurality of functional units configurable to operate in a vector operation mode and a scalar operation mode, the parallel vector unit includes means for tightly coupling a plurality of the functional units to perform an operation specified by a current instruction; wherein under a vector operation mode the parallel vector unit performs, in parallel, a single vector operation on a plurality of data elements, the operations performed on the plurality of data elements each being performed by a different functional unit of the parallel vector unit; and wherein under a scalar operation mode the parallel vector unit performs a scalar operation on a data element received from the one or more register files in a functional unit within the parallel vector unit.
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| Background / Summary: |
Show background / summary
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| Drawing Descriptions: |
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| Description: |
Show description
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| Forward References: |
Show 7 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other Abstract Info: |
DERABS C2003-392617
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| Other References: |
M. Tremblay et al. “VIS Speeds New Media Processing”, IEEE Micro,Aug. 1996 pp. 10-22.
R. Lee, “Multimedia Enhancements for PA-RISC Processors” Hewlett-Packard Company, HotChips VI, 8/94 pp. 7.3.1-7.3.10 (183-191).
K. Diefendoroff et al. “How Multimedia Workloads Will change Processor Design”, Computer, Sep. 1997 pp. 43-45.
(4 pages)
[ISI abstract]
T. M Conte et al. “Challenges to Combining General-Purpose and Multimedia Processors” Dec. 1997, Computer IEEE pp. 33-37.
(6 pages)
Cited by 5 patents
[ISI abstract]
R. B. Lee “Subword Parallelism with MAX-2” Hewlett Packard IEEE Micro, Aug. 1996 pp. 51-59.
A. Peleg et al. “MMX Technology Extension to the Intel Architecture” IEEE Micro Aug. 1996 pp. 42-50.
(9 pages)
Cited by 10 patents
[ISI abstract]
A. Peleg et al., “Intel MMX for Multimedia PCs” Communications of the ACMM Jauary 1997/vol. 40, No. 1 pp. 25-38.
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| Continuity Data: |
| Application Number | Filed | Notes |
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US2001000929805 | 2001-08-14 | is a
related to the prior publication |
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US20030037221A1 issued 2003-02-20 Processor implementation having unified scalar and SIMD datapath
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