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Title: |
US6859109:
Double-data rate phase-locked-loop with phase aligners to reduce clock skew
[ Derwent Title ]

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Country: |
US United States of America

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Inventor: |
Leung, Gerry C. T.; Hong Kong, China
Luong, Howard C.; Renton, WA, United States of America

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Assignee: |
Pericom Semiconductor Corp., San Jose, CA, United States of America
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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Published / Filed: |
2005-02-22
/ 2003-05-27

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Application Number: |
US2003000250000

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IPC Code: |
Advanced:
H03B 5/12;
H03L 7/099;
H03L 7/183;
Core:
H03B 5/08;
H03L 7/08;
H03L 7/16;
IPC-7:
H03B 27/00;

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ECLA Code: |
H03B5/12D; H03L7/099; H03L7/183;

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U.S. Class: |
Current:
331/046;
327/141;
327/147;
327/150;
327/151;
327/156;
327/159;
331/001.A;
331/045;
331/117.R;
331/117.FE;
331/167;
331/185;
Original:
331/046;
331/185;
331/001.A;
331/117.R;
331/117.FE;
331/167;
331/045;
327/141;
327/147;
327/150;
327/151;
327/156;
327/159;

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Field of Search: |
331/1 A,25,45,46,117 R,117 FE,167
327/141,147,150,151,156,159
375/376

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Priority Number: |
| 2003-05-27 |
US2003000250000 |

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Abstract: |
A phase-locked loop (PLL) has an analog divider in the feedback path that receives either the in-phase or quadrature-phase pair of outputs from a voltage-controlled oscillator (VCO) while the other pair, 90-degree out-of-phase, of outputs from the VCO is used for the PLL output. Phases between the PLL's input and output are inherently aligned. The analog output of the analog divider is converted to a digital clock signal and applied to a cascade of digital dividers to generate a reduced feedback clock. The reduced feedback clock is applied to the D input and the digital clock signal is applied to the clock input of a pseudo D-flip-flop that drives the feedback input of a phase-frequency detector that drives the charge pump to the VCO input. Another cascade of digital dividers and pseudo D-flip-flop re-align the reference clock input to the phase-frequency detector. Analog and digital re-alignment circuits reduce internal skew.

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Attorney, Agent or Firm: |
Auvinen, Stuart T. ;

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Primary / Asst. Examiners: |
Kinkead, Arnold;

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INPADOC Legal Status: |
Show legal status actions

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Family: |
None

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First Claim:
Show all 20 claims |
1. A phase-aligning phase-locked loop (PLL) comprising: a phase-frequency detector having a reference input and a feedback input, for determining phase differences between the reference input and the feedback input; a loop filter for generating a control voltage; a charge pump, controlled by the phase-frequency detector, for charging and discharging the loop filter to adjust the control voltage; a voltage-controlled oscillator (VCO) generating multi-phase output clocks having an output frequency controlled by the control voltage from the loop filter; an analog divider, receiving at least two of the multi-phase output clocks from the VCO, and generating a divided analog feedback clock having a feedback frequency that is the output frequency divided by a positive power of two; a clock buffer, receiving the divided analog feedback clock, for generating a digital feedback clock; a feedback digital divider, receiving the digital feedback clock, for generating a final feedback clock having a final feedback frequency that is the feedback frequency divided by a positive power of two; and a feedback flip-flop, receiving the final feedback clock and clocked by the digital feedback clock, for generating a phase-aligned feedback clock to the feedback input of the phase-frequency detector; whereby the analog divider and digital divider are in a feedback path.

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Background / Summary: |
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Drawing Descriptions: |
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Description: |
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Forward References: |
Show 2 U.S. patent(s) that reference this one

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Foreign References: |
None

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Other References: |
Joo-Ho Lee, et al., “A 330 MHz low-jitter and fast-locking direct skew compensation DLL” IEEE International Solid-State Circuits Conference, 2000, pp. 352-353.
Saeki, T, et al., “A direct-skew-detect synchronous mirror delay for application-specific integrated circuits” JSSC, vol. 34, No. 3, pp. 372-379, Mar. 1999.
(8 pages)
Cited by 12 patents
[ISI abstract]
Wang et al., “A 500 Mb/s/pin quadruple data rate SDRAM interface using a skew cancellation technique,” IEEE JSSC, vol. 36, No. 4, pp. 648-657 Apr. 2001.
(10 pages)
Cited by 2 patents
[ISI abstract]

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