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Title: US6859109: Double-data rate phase-locked-loop with phase aligners to reduce clock skew
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Country: US United States of America

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13 pages

 
Inventor: Leung, Gerry C. T.; Hong Kong, China
Luong, Howard C.; Renton, WA, United States of America

Assignee: Pericom Semiconductor Corp., San Jose, CA, United States of America
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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Published / Filed: 2005-02-22 / 2003-05-27

Application Number: US2003000250000

IPC Code: Advanced: H03B 5/12; H03L 7/099; H03L 7/183;
Core: H03B 5/08; H03L 7/08; H03L 7/16;
IPC-7: H03B 27/00;

ECLA Code: H03B5/12D; H03L7/099; H03L7/183;

U.S. Class: Current: 331/046; 327/141; 327/147; 327/150; 327/151; 327/156; 327/159; 331/001.A; 331/045; 331/117.R; 331/117.FE; 331/167; 331/185;
Original: 331/046; 331/185; 331/001.A; 331/117.R; 331/117.FE; 331/167; 331/045; 327/141; 327/147; 327/150; 327/151; 327/156; 327/159;

Field of Search: 331/1 A,25,45,46,117 R,117 FE,167 327/141,147,150,151,156,159 375/376

Priority Number:
2003-05-27  US2003000250000

Abstract:     A phase-locked loop (PLL) has an analog divider in the feedback path that receives either the in-phase or quadrature-phase pair of outputs from a voltage-controlled oscillator (VCO) while the other pair, 90-degree out-of-phase, of outputs from the VCO is used for the PLL output. Phases between the PLL's input and output are inherently aligned. The analog output of the analog divider is converted to a digital clock signal and applied to a cascade of digital dividers to generate a reduced feedback clock. The reduced feedback clock is applied to the D input and the digital clock signal is applied to the clock input of a pseudo D-flip-flop that drives the feedback input of a phase-frequency detector that drives the charge pump to the VCO input. Another cascade of digital dividers and pseudo D-flip-flop re-align the reference clock input to the phase-frequency detector. Analog and digital re-alignment circuits reduce internal skew.

Attorney, Agent or Firm: Auvinen, Stuart T. ;

Primary / Asst. Examiners: Kinkead, Arnold;

INPADOC Legal Status: Show legal status actions

Family: None

First Claim:
Show all 20 claims
    1. A phase-aligning phase-locked loop (PLL) comprising:

a phase-frequency detector having a reference input and a feedback input, for determining phase differences between the reference input and the feedback input;

a loop filter for generating a control voltage;

a charge pump, controlled by the phase-frequency detector, for charging and discharging the loop filter to adjust the control voltage;

a voltage-controlled oscillator (VCO) generating multi-phase output clocks having an output frequency controlled by the control voltage from the loop filter;

an analog divider, receiving at least two of the multi-phase output clocks from the VCO, and generating a divided analog feedback clock having a feedback frequency that is the output frequency divided by a positive power of two;

a clock buffer, receiving the divided analog feedback clock, for generating a digital feedback clock;

a feedback digital divider, receiving the digital feedback clock, for generating a final feedback clock having a final feedback frequency that is the feedback frequency divided by a positive power of two; and

a feedback flip-flop, receiving the final feedback clock and clocked by the digital feedback clock, for generating a phase-aligned feedback clock to the feedback input of the phase-frequency detector;

whereby the analog divider and digital divider are in a feedback path.



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Forward References: Show 2 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (2)   |   Backward references (18)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 19pp US5608357  1997-03 Ta et al.  VLSI Technology, Inc. High speed phase aligner with jitter removal
Buy PDF- 14pp US6111470  2000-08 Dufour  Philips Electronics North America Corporation Phase-locked loop circuit with charge pump noise cancellation
Buy PDF- 111pp US6114890  2000-09 Okajima et al.  Fujitsu Limited Skew-reduction circuit
Buy PDF- 12pp US6222895  2001-04 Larsson  Agere Systems Guardian Corp. Phase-locked loop (PLL) circuit containing a sampled phase detector with reduced jitter
Buy PDF- 9pp US6265919  2001-07 Guisante et al.  Lucent Technologies Inc. In phase alignment for PLL's
Buy PDF- 11pp US6320436  2001-11 Fawcett et al.  STMicroelectronics Limited Clock skew removal apparatus
Buy PDF- 8pp US6346838  2002-02 Hwang et al.  Taiwan Semiconductor Manufacturing Corporation Internal offset-canceled phase locked loop-based deskew buffer
Buy PDF- 10pp US6373301  2002-04 Chen et al.  Silicon Integrated Systems Corporation Fast-locking dual rail digital delayed locked loop
Buy PDF- 18pp US6437620  2002-08 Singor  Broadcom Corporation Circuit and method for multi-phase alignment
Buy PDF- 10pp US6445234  2002-09 Yoon et al.  Hyundai Electronics Industries Co., Ltd. Apparatus and method for accelerating initial lock time of delayed locked loop
Buy PDF- 9pp US6466069  2002-10 Rozenblit et al.  Conexant Systems, Inc. Fast settling charge pump
Buy PDF- 12pp US6466074  2002-10 Vakil et al.  Intel Corporation Low skew minimized clock splitter
Buy PDF- 10pp US6469584  2002-10 Eker et al.  Applied Micro Circuits Corporation Phase-locked loop system and method using an auto-ranging, frequency sweep window voltage controlled oscillator
Buy PDF- 7pp US6476594  2002-11 Roisen  LSI Logic Corporation Method and apparatus for testing high frequency delay locked loops
Buy PDF- 18pp US6476652  2002-11 Lee et al.  Hynix Semiconductor Inc. Delay locked loop for use in synchronous dynamic random access memory
Buy PDF- 20pp US6476656  2002-11 Dally et al.  Velio Communications, Inc. Low-power low-jitter variable delay timing circuit
Buy PDF- 15pp US6477657  2002-11 Kurd et al.  Intel Corporation Circuit for I/O clock generation
Buy PDF- 10pp US6477688  2002-11 Wallace   Logic equivalence leveraged placement and routing of an IC design
       
Foreign References: None

Other References:
  • Joo-Ho Lee, et al., “A 330 MHz low-jitter and fast-locking direct skew compensation DLL” IEEE International Solid-State Circuits Conference, 2000, pp. 352-353.
  • Saeki, T, et al., “A direct-skew-detect synchronous mirror delay for application-specific integrated circuits” JSSC, vol. 34, No. 3, pp. 372-379, Mar. 1999. (8 pages) Cited by 12 patents [ISI abstract]
  • Wang et al., “A 500 Mb/s/pin quadruple data rate SDRAM interface using a skew cancellation technique,” IEEE JSSC, vol. 36, No. 4, pp. 648-657 Apr. 2001. (10 pages) Cited by 2 patents [ISI abstract]


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