a phase-locked loop having a voltage-controlled oscillator (VCO) that generates four phase clocks having a same input frequency but having differing phase offsets;

a first divide-by-X-plus-two circuit, receiving a first phase clock of the four phase clocks, for generating a first divided-by-X-plus-two signal that has a frequency being the input frequency divided by (X+2), the first divided-by-X-plus-two signal being synchronous to the first phase clock;

a second divide-by-X-plus-two circuit, wherein X-plus-two is twice X, receiving a second phase clock of the four phase clocks, for generating a second divided-by-X-plus-two signal that has a frequency being the input frequency divided by (X+2), the second divided-by-X-plus-two signal being synchronous to the second phase clock;

a third divide-by-X-plus-two circuit, wherein X-plus-two is twice X, receiving a third phase clock of the four phase clocks, for generating a third divided-by-X-plus-two signal that has a frequency being the input frequency divided by (X+2), the third divided-by-X-plus-two signal being synchronous to the third phase clock;

a fourth divide-by-X-plus-two circuit, wherein X-plus-two is twice X, receiving a fourth phase clock of the four phase clocks, for generating a fourth divided-by-X-plus-two signal that has a frequency being the input frequency divided by (X+2), the fourth divided-by-X-plus-two signal being synchronous to the fourth phase clock; and

a frequency doubler, receiving the first, second, third, and fourth divided-by-X-plus-two signals, for generating an output clock having an output frequency that is the input frequency divided by X.5,

whereby the output clock is generated from the four phase clocks from the voltage-controlled oscillator.