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Title: US6886148: Method and system for displaying VLSI layout data
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Country: US United States of America

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34 pages

 
Inventor: Solomon, Jeffrey M.; Millbrae, CA, United States of America

Assignee: The Board of Trustees of the Leland Stanford Jr. University, Stanford, CA, United States of America
other patents from STANFORD UNIVERSITY (675809) (approx. 1,667)
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Published / Filed: 2005-04-26 / 2002-12-10

Application Number: US2002000314957

IPC Code: Advanced: G06F 17/50; G06T 17/40;
Core: more...
IPC-7: G06F 17/50;

ECLA Code: G06F17/50L; G06T17/40;

U.S. Class: 716/011; 716/003;

Field of Search: 716/011,3

Priority Number:
2002-12-10  US2002000314957
2001-07-10  US2001000901028
2001-03-23  US2001000278001P

Abstract:     A VLSI layout editor and method for using same that increases display and re-display speed and accuracy uses properties inherent to VLSI layouts that allows them to be displayed efficiently and accurately independent of the canonical expression of the VLSI design. The VLSI layout editor and methods for using same use precomputed images that each represent a portion of the VLSI layout, a hierarchy cache that includes multiple LOD versions of selected sub-designs in the pre-computed images, and selected direct determination of the viewable representation from the canonical expression for at least one LOD. Apparatus and methods according to the present invention can render a particular type of data whose canonical form is smaller than its corresponding displayed image thereof when the displayed image has geometric properties that allow heuristics and rasterization for dynamic and accurate expansion using selected combined techniques. Texture mapping and mipmapping can be used to accurately reduce, expand and reorder layers in a viewable image expanded from a canonical expression of the VLSI layout.

Attorney, Agent or Firm: Fleshner & Kim, LLP ;

Primary / Asst. Examiners: Tran, M.;

INPADOC Legal Status: None          Buy Now: Family Legal Status Report

       
Related Applications:
Application Number Filed Patent Pub. Date  Title
US2001000901028 2001-07-10    2002-12-10  Method and system for displaying VLSI layout data


       
Family: Show 5 known family members

First Claim:
Show all 47 claims
    1. An apparatus, comprising:

a first memory that stores a representation of an integrated circuit (IC) layout having a plurality of layers; and

a controller coupled to the first memory that generates a displayable representation of ordered layers of the IC layout that tracks changes in a user viewpoint, wherein the displayable representation comprises a precomputed image that represents a part of the IC layout, and wherein the precomputed image is used in two or more user viewpoints.



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Forward References: Show 2 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (2)   |   Backward references (4)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 9pp US4783749  1988-11 Duzy et al.  Siemens Aktiengesellschaft Basic cell realized in the CMOS technique and a method for the automatic generation of such a basic cell
Buy PDF- 17pp US5086477  1992-02 Yu et al.  Northwest Technology Corp. Automated system for extracting design and layout information from an integrated circuit
Buy PDF- 18pp US5481717  1996-01 Gaboury  Kabushiki Kaisha Toshiba Logic program comparison method for verifying a computer program in relation to a system specification
Buy PDF- 26pp US5760783  1998-06 Migdal et al.  Silicon Graphics, Inc. Method and system for providing texture using a selected portion of a texture map
       
Foreign References: None

Other Abstract Info: DERABS C2003-522596

Other References:
  • IC Station Stream View by Mentor Graphics Product Description Data Sheet, 2 pp.
  • Virtuoso Layout Editor by Cadence Design Systems, Inc. Product Description Data Sheet, 3 pp.


  • Continuity Data:
    Application Number Filed Notes

    US2002000314957 2002-12-10  is a related to the prior publication
         US20030076722A1 issued 2003-04-24  Method and system for displaying VLSI layout data

    >US2002000314957< 2002-12-10  is a continuation of
    US2001000901028  2001-07-10   (granted)
         US6493858 issued 2002-12-10   Method and system for displaying VLSI layout data

    >US2002000314957<   is a continuation of
    US2001000901028  2001-07-10
         US6493858 issued 2002-12-10   Method and system for displaying VLSI layout data

    US2002000314957 2002-12-10  is a non-provisional of provisional
    US2001000278001P  2001-03-23


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