 |
|
|
|
|
|
 Title: |
US6907477:
Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors
[ Derwent Title ]
|
| Country: |
US United States of America
|
| |
| Inventor: |
Altman, Erik R.; Danbury, CT, United States of America
Capek, Peter G.; Ossining, NY, United States of America
Gschwind, Michael; Yorktown, NY, United States of America
Hofstee, Harm Peter; Austin, TX, United States of America
Kahle, James Allan; Austin, TX, United States of America
Nair, Ravi; Briarcliff Manor, NY, United States of America
Sathaye, Sumedh Wasudeo; Fishkill, NY, United States of America
Wellman, John-David; Peekskill, NY, United States of America
|
| Assignee: |
International Business Machines Corporation, Armonk, NY, United States of America
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
News, Profiles, Stocks and More about this company
|
| Published / Filed: |
2005-06-14
/ 2004-02-19
|
| Application Number: |
US2004000782044
|
| IPC Code: |
Advanced:
G06F 12/10;
Core:
more...
IPC-7:
G06F 9/28;
G06F 13/28;
G06F 13/368;
|
| ECLA Code: |
G06F12/10L;
|
| U.S. Class: |
710/022;
710/026;
711/147;
711/153;
711/173;
711/202;
711/203;
711/205;
711/206;
711/207;
711/208;
|
| Field of Search: |
711/001,5,6,147,150,153,173,202,205,206,207,208,209
712/001,14,20,27,22,26,62,74
|
| Priority Number: |
|
| Abstract: |
A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.
|
| Attorney, Agent or Firm: |
Voigt, Jr., Robert A. ;
Winstead Sechrest & Minick P.C. ;
Salys, Casimer K. ;
|
| Primary / Asst. Examiners: |
Peikari, B. James;
|
| Maintenance Status: |
E1 Expired Check current status
|
| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
|
|
|
|
|
|
|
| Parent Case: |
CROSS REFERENCE TO RELATED APPLICATIONS
The present invention is related to the following U.S. Patent Applications which are incorporated herein by reference:
Ser. No. 09/736,356, filed on Dec. 14, 2000, now U.S. Pat. No. 6,820,142.
Ser. No. 09/736,582, filed on Dec. 14, 2000.
|
| Family: |
Show 6 known family members
|
First Claim:
Show all 11 claims |
1. A system, comprising: (a) a shared memory; and (b) two or more processing elements coupled to said shared memory, wherein two or more of said processing elements comprise: (1) a processing unit, wherein said processing unit comprises a first address translation mechanism; (2) a direct memory access controller coupled to said processing unit, wherein said direct memory access controller comprises a second address translation mechanism; and (3) at least one attached processing unit coupled to said direct memory access controller, wherein said at least one attached processing unit does not comprise an address translation mechanism.
|
| Background / Summary: |
Show background / summary
|
| Drawing Descriptions: |
Show drawing descriptions
|
| Description: |
Show description
|
| Forward References: |
Show 2 U.S. patent(s) that reference this one
|
|
