 |
|
|
|
|
|
 Title: |
US6970982:
Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions
[ Derwent Title ]
|
| Country: |
US United States of America
|
| |
| Inventor: |
Altman, Erik R.; Danbury, CT, United States of America
Capek, Peter G.; Ossining, NY, United States of America
Gschwind, Michael Karl; Yorktown, NY, United States of America
Hofstee, Harm Peter; Austin, TX, United States of America
Kahle, James Allan; Austin, TX, United States of America
Nair, Ravi; Briarcliff Manor, NY, United States of America
Sathaye, Sumedh Wasudeo; Fishkill, NY, United States of America
Wellman, John-David; Peekskill, NY, United States of America
|
| Assignee: |
International Business Machines Corporation, Armonk, NY, United States of America
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
News, Profiles, Stocks and More about this company
|
| Published / Filed: |
2005-11-29
/ 2003-10-01
|
| Application Number: |
US2003000676540
|
| IPC Code: |
Advanced:
G06F 12/10;
Core:
more...
IPC-7:
G06F 13/00;
|
| ECLA Code: |
G06F12/10L;
|
| U.S. Class: |
711/141;
711/146;
711/124;
709/213;
|
| Field of Search: |
711/124,141,144,146,203,205,207,208
709/213,216,217,219
718/001
|
| Priority Number: |
|
| Abstract: |
A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.
|
| Attorney, Agent or Firm: |
Voight, Jr., Robert A. ;
Winstead Sechrest & Minick P.C. ;
Salys, Casimer K. ;
|
| Primary / Asst. Examiners: |
Peikari, B. James;
|
| INPADOC Legal Status: |
None
Family Legal Status Report
|
|
|
|
|
|
|
| Parent Case: |
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a divisional application of U.S. patent application Ser. No. 09/736,585, entitled “Symmetric Multi-Processing System,” filed Dec. 14, 2000, now U.S. Pat. No. 6,779,049. This application claims priority benefits to U.S. patent application Ser. No. 09/736,585.
|
| Family: |
Show 6 known family members
|
First Claim:
Show all 12 claims |
1. A method for maintaining Translation Lookaside Buffer (TLB) consistency in a system comprising a shared memory and a plurality of processing elements coupled to said shared memory, wherein each of said plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units, wherein each of said plurality of direct memory access controllers comprises a TLB, the method comprising the steps of: invalidating a copy of a page table entry that was updated in a particular TLB of a direct memory access controller associated with a particular processing unit by said particular processing unit; broadcasting a TLB invalided entry instruction to each of said plurality of processing units other than said particular processing unit by said particular processing unit; determining whether to invalidate any entries in the TLB's associated with each of said plurality of direct memory access controllers other than the direct memory access controller associated with said particular processing unit; and issuing a synchronization instruction to each of said plurality of processing units other than said particular processing unit by said particular processing unit.
|
| Background / Summary: |
Show background / summary
|
| Drawing Descriptions: |
Show drawing descriptions
|
| Description: |
Show description
|
| Forward References: |
Show 2 U.S. patent(s) that reference this one
|
|
