a plurality of control signals in the clock-transmitting chip, the plurality of control signals for controlling operation of the clock-receiving chip;

a plurality of received control signals in the clock-receiving chip, the plurality of received control signals for controlling operation of the clock-receiving chip;

a transmit clock in the clock-transmitting chip;

a differential driver in the clock-transmitting chip, receiving the transmit clock and driving a true differential clock line and a complement differential clock line with opposite states during normal operation when the transmit clock is sent from the clock-transmitting chip to the clock-receiving chip over the true and complement differential clock lines;

a differential receiver in the clock-receiving chip, the differential receiver receiving the true and complement differential clock lines and generating a receive clock;

an encoder in the clock-transmitting chip that receives the plurality of control signals, for outputting a pre-defined sequence on a blocking signal to the differential driver, the pre-defined sequence indicating a change in one of the plurality of control signals;

wherein the differential driver alters the true and complement differential lines in the pre-defined sequence to indicate a control signal;

a decoder, in the clock-receiving chip, for determining the pre-defined sequence when the true and complement differential lines have been altered, and for changing one of the received control signals in the clock-receiving chip that corresponds to the pre-defined sequence; and

a phase-locked loop (PLL) in the clock-receiving chip that has the receive clock as an input, and outputs an internal clock for use by the clock-receiving chip,

wherein when the true and complement differential clock lines are altered, causing the receive clock to miss a clock pulse, the PLL continues to pulse the internal clock without missing a clock pulse;

wherein the pre-defined sequence include a first number of altered clock pulses, followed by a second number of un-altered clock pulses, followed by a third number of altered clock pulses;

wherein the first, second, and third numbers are at least one;

whereby changes in the plurality of control signals in the clock-transmitting chip are sent over the true and complement differential clock lines encoded in a pre-defined sequence and whereby alterations to the true and complement differential clock lines are filtered out by the PLL.