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 Title: |
US7051168:
Method and apparatus for aligning memory write data in a microprocessor
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Gschwind, Michael K.; Yorktown, NY, United States of America
Hopkins, Martin E.; Chappaqua, NY, United States of America
Hofstee, H. Peter; Austin, TX, United States of America
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| Assignee: |
International Business Machines Corporation, Armonk, NY, United States of America
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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| Published / Filed: |
2006-05-23
/ 2001-08-28
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| Application Number: |
US2001000940911
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| IPC Code: |
Advanced:
G06F 9/30;
G06F 9/312;
G06F 9/315;
G06F 9/38;
G06F 12/00;
Core:
more...
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| ECLA Code: |
G06F9/30R4; G06F9/312; G06F9/315; G06F9/38D;
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| U.S. Class: |
711/154;
711/155;
712/204;
712/300;
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| Field of Search: |
711/154,155,171,201
712/204,300
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| Priority Number: |
| 2001-08-28 |
US2001000940911 |
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| Abstract: |
There is provided a method for aligning and inserting data elements into a memory based upon an instruction sequence consisting of one or more alignment instructions and a single store instruction. Given a data item that includes a data element to be stored, the method includes the step of aligning the data element in another memory with respect to a predetermined position in the memory, in response to the one or more alignment instructions. A mask is dynamically generated to enable writing of memory bit lines that correspond to the aligned data element. The memory bit lines are written to the memory under a control of the mask. The generating and writing steps are performed in response to the single store instruction.
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| Attorney, Agent or Firm: |
F. Chau & Associates, LLC ;
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| Primary / Asst. Examiners: |
Peikari, B. James; Choi, Woo H.
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Family: |
Show 2 known family members
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First Claim:
Show all 22 claims |
1. A method for aligning and inserting data elements into a first memory based upon an instruction sequence consisting of one or more alignment instructions and a single store instruction, comprising the steps of: given a data item that includes a data element to be stored, aligning the data element in a second memory with respect to a predetermined position in the first memory, in response to the one or more alignment instructions; dynamically generating a mask to enable writing of memory bit lines that correspond to the aligned data element; and writing the memory bit lines to the first memory under a control of the mask, wherein said generating and writing steps are performed in response to the single store instruction, wherein the method is performed without merging.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 6 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other References: |
John L. Hennessy, “VLSI Processor Architecture,” Dec. 1984, IEEE Transactions On Computers, vol. C-33, No. 12, pp. 1221-1246.
(26 pages)
Cited by 9 patents
Richard L. Sites, “Alpha AXP Architecture,” Feb. 1993, Communications of the ACM, vol. 36., No. 2, pp. 33-44.
Patent Application entitled “Processor Implementation having Unified Scalar and SIMD Datapath,” filed on Aug. 14, 2001.
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| Continuity Data: |
| Application Number | Filed | Notes |
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US2001000940911 | 2001-08-28 | is a
related to the prior publication |
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US20030056064A1 issued 2003-03-20 Method and apparatus for aligning memory write data in a microprocessor
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