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Title: US7093147: Dynamically selecting processor cores for overall power efficiency
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Country: US United States of America

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9 pages

 
Inventor: Farkas, Keith; San Carlos, CA, United States of America
Jouppi, Norman P.; Palo Alto, CA, United States of America
Mayo, Robert N.; Mountain View, CA, United States of America
Ranganathan, Parthasarathy; Palo Alto, CA, United States of America

Assignee: Hewlett-Packard Development Company, L.P., Houston, TX, United States of America
other patents from HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (815532) (approx. 1,981)
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Published / Filed: 2006-08-15 / 2003-04-25

Application Number: US2003000423397

IPC Code: Advanced: G06F 1/32;
Core: more...

ECLA Code: G06F9/50L2; G06F1/32P;

U.S. Class: 713/320;

Field of Search: 713/320

Priority Number:
2003-04-25  US2003000423397

Abstract:     A computer system for conserving operating power includes a number of computer hardware processor cores that differ amongst themselves in at least in their respective operating power requirements and processing capabilities. A monitor gathers performance metric information from each of the computer hardware processor cores that is specific to a particular run of application software then executing. A workload transfer mechanism transfers the executing application software to a second computer hardware processor core in a search for reduced operating power. A transfer delay mechanism is connected to delay a subsequent transfer of the executing application software if the system operating power may be conserved by such delay.

Primary / Asst. Examiners: Cao, Chun; Wang, Albert

INPADOC Legal Status: None          Buy Now: Family Legal Status Report

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First Claim:
Show all 16 claims
    1. A multi-core processor computer system for conserving average operating power, comprising:

a plurality of computer hardware processor cores that differ amongst themselves in at least their respective operating power requirements and processing capabilities;

a monitor for gathering performance and power metric information from a first one of said computer hardware processor cores that is running software; and

a workload transfer and control mechanism connected to the plurality of computer hardware processor cores and to the monitor to select a second one of said processing cores to run the software,

wherein the monitor gathers performance and power metric information from the second one of the processing cores, and

wherein the workload transfer and control mechanism compares the performance and power metric information from the second processing core with the performance and power metric information from the first processing core, and selects one of the first and second processing cores to continue running the software based on the comparison.



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Forward References: Show 9 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (9)   |   Backward references (2)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 17pp US5913068  1999-06 Matoba  Kabushiki Kaisha Toshiba Multi-processor power saving system which dynamically detects the necessity of a power saving operation to control the parallel degree of a plurality of processors
Buy PDF- 14pp US6804632  2004-10 Orenstien et al.  Intel Corporation Distribution of processing activity across processing hardware based on power consumption considerations
       
Foreign References: None

Other References:
  • R. Kumar et al., “Processor Power Reduction Via Single-ISA Heterogeneous Multi-core Architectures”, In Computer Architecture Letters, vol. 2, Apr. 2003.
  • R. Kumar et al., “A Multi-Core Approach to Addressing the Energy-Complexity Problem in Microprocessors”, In Work on Complexity-Effective Design, Jun. 2003.


  • Continuity Data:
    Application Number Filed Notes

    US2003000423397 2003-04-25  is a related to the prior publication
         US20040215987A1 issued 2004-10-28  Dynamically selecting processor cores for overall power efficiency


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