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 Title: |
US7100026:
System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Dally, William J.; Stanford, CA, United States of America
Rixner, Scott; Spring, TX, United States of America
Owens, John D.; Emeryville, CA, United States of America
Kapasi, Ujval J.; Santa Clara, CA, United States of America
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| Assignee: |
The Massachusetts Institute of Technology, Cambridge, MA, United States of America
The Board of Trustees of the Leland Stanford Junior University, Palo Alto, CA, United States of America
other patents from MASSACHUSETTS INSTITUTE OF TECHNOLOGY (357270) (approx. 2,706)
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| Published / Filed: |
2006-08-29
/ 2001-05-30
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| Application Number: |
US2001000871301
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| IPC Code: |
Advanced:
G06F 7/38;
G06F 9/30;
G06F 9/302;
G06F 9/38;
G06F 15/80;
Core:
G06F 15/76;
more...
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| ECLA Code: |
G06F9/30R2; G06F9/302; G06F9/38T; G06F15/80B;
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| U.S. Class: |
Current:
712/222;
712/004;
712/008;
712/022;
712/E09.017;
712/E09.024;
712/E09.071;
718/105;
Original:
712/222;
712/004;
712/008;
712/022;
718/105;
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| Field of Search: |
712/002,4-9,22,220-224
718/105
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| Priority Number: |
| 2001-05-30 |
US2001000871301 |
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| Abstract: |
A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be processed at full processor efficiency without cycles wasted due to branch latency. Data to be processed are divided into two groups based on whether or not they satisfy a given condition by, e.g., steering each to one of two index vectors. Once the data have been segregated in this way, subsequent processing can be performed without conditional operations, processor cycles wasted due to branch latency, incorrect speculation or execution of unnecessary instructions due to predication. Other examples of conditional operations include combining one or more input vectors into a single output vector based on a condition vector, conditional vector switching, conditional vector combining, and conditional vector load balancing.
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| Attorney, Agent or Firm: |
Crawford Maunu PLLC ;
Crawford, Robert J. ;
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| Primary / Asst. Examiners: |
Tsai, Henry W. H.; Meonske, Tonia L.
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| Maintenance Status: |
CC Certificate of Correction issued
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| INPADOC Legal Status: |
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| Parent Case: |
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to and claims priority under 35 U.S.C. §120 from U.S. patent application Ser. No. 09/152,944, incorporated herein by reference.
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| Family: |
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First Claim:
Show all 14 claims |
1. A method of performing a distributed conditional vector input operation in a processor, the method comprising: generating a plurality of electrical signals as a condition vector representative of whether individual arithmetic clusters in a plurality of arithmetic clusters are to receive data; distributing a plurality of electrical signals as an input vector having input vector elements to arithmetic clusters in the plurality of arithmetic clusters for which a corresponding portion of the condition vector is equal to a predetermined value, a length of the condition vector being greater than a length of the input vector; using the arithmetic clusters to process the input vector elements distributed thereto; and assembling the processed input vector elements to form an output vector having a length equal to that of the condition vector.
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| Background / Summary: |
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| Description: |
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| Forward References: |
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