a substrate containing wiring traces for conducting signals;

first contact pads along a first edge of the substrate, the first contact pads for mating with a memory module socket on a motherboard;

a test socket, mounted to the substrate, for receiving a memory module during testing and programming;

an intercepting electrically erasable and programmable read-only memory (EEPROM) chip, mounted on the substrate, the intercepting EEPROM chip for being programmed with a configuration for the memory module inserted into the test socket, the configuration from the intercepting EEPROM chip being read by the motherboard before testing of the memory module inserted into the test socket;

wherein the wiring traces on the substrate include lines carrying address, data, and controls signals from the motherboard that are passed through to the test socket at pads for connecting to memory chips on the memory module;

wherein the wiring traces on the substrate include a first device-address line and a second device-address line;

wherein the first device-address line connects to a device-address input of the intercepting EEPROM chip;

wherein the second device-address line connects to the test socket at a pad location for connecting to a device-address input of a module EEPROM chip on the memory module; and

device-address intercept means, on the substrate, for causing the first device-address line and the second device-address line to have opposite states, wherein when the first device-address line is high then the second device-address line is low, or when the first device-address line is low then the second device-address line is high,

whereby the extender card alters device addresses so that the second device-address line to the module EEPROM chip and the first device-address line to the intercepting EEPROM chip have opposite states.