a reference-clock input for receiving a reference clock from an external clock source;

a feedback clock;

a phase detector that receives the reference clock and the feedback clock;

a filter capacitor on a filter node;

a charge pump, responsive to a phase difference detected by the phase detector, for charging and discharging the filter capacitor on the filter node;

wherein the charge pump comprises:

a first source transistor having a gate receiving a mode signal that indicates when the PLL is operating;

a first bias transistor having a gate receiving a bias voltage;

wherein the first source transistor and the first bias transistor are in series between a power supply and the filter node;

a second source transistor having a gate receiving a mode signal that indicates when the PLL is operating;

a second bias transistor having a gate receiving a second bias voltage;

wherein the second source transistor and the second bias transistor are in series between a ground and the filter node;

a voltage-controlled oscillator (VCO) having the filter node as an input and outputting a clock having a frequency that depends on a filter voltage of the filter node;

wherein the feedback clock is output by the VCO or is derived from the clock output by the VCO;

a test current generator, activated during a leakage test mode, for driving a test current onto the filter node; and

a test comparator, receiving a reference voltage and coupled to the filter node, for comparing the filter voltage to the reference voltage to determine when the test current is able to charge the filter capacitor and to determine when the test current is unable to charge the filter capacitor beyond the reference voltage;

wherein the test comparator outputs a result signal that indicates a leaky filter capacitor when the filter voltage cannot reach the reference voltage,

whereby the filter capacitor within the testable PLL is tested for leakage by the test current generator and the test comparator.