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Title: US7149956: Converging error-recovery for multi-bit-incrementing gray code
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Country: US United States of America

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12 pages

 
Inventor: Lu, Hui; Union City, CA, United States of America

Assignee: Pericom Semiconductor Corp., San Jose, CA, United States of America
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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Published / Filed: 2006-12-12 / 2004-02-09

Application Number: US2004000708095

IPC Code: Advanced: H03M 7/16;
Core: H03M 7/14;

ECLA Code: H03M7/16;

U.S. Class: 714/809; 341/097; 341/098; 377/034; 714/819;

Field of Search: 341/094,97-98 377/034 / H03M 7/16

Priority Number:
2004-02-09  US2004000708095

Abstract:     An L-bit gray-code input value can change by more N bits at a time. The lower N bits of the input are stored as a received least-significant-bits (LSB) while the upper bits are stored as a received most-significant-bits (MSB). A stored register holds the corrected, stored MSB and LSB for use by the receiver. When the received and stored MSB's mis-match, the new MSB is stored and the stored LSB is generated so that the stored register contains the smallest possible value with the new MSB. When the received and stored MSB's match, the full L bits are compared. When the received word is larger than the stored word, the largest mis-matching bit in the LSB is found, and bits above this are copied from the received LSB to the stored register, while lower bits are generated to produce the lowest value. Repeating the process converges the result.

Attorney, Agent or Firm: gPatent LLC ; Auvinen, Stuart T. ;

Primary / Asst. Examiners: Dildine, R. Stephen;

INPADOC Legal Status: Show legal status actions

Family: None

First Claim:
Show all 20 claims
    1. A gray-code error corrector comprising:

an input for receiving input gray-code words in a received sequence, the input gray-code words belonging to a full sequence of gray-code values, wherein successive gray-code values in the full sequence have only one bit difference, wherein the received sequence contains successively-received words that differ by a maximum of N bits, wherein N is a whole number of two or more, wherein the successively-received words differ in value by a maximum of 2N−1,

a received register, coupled to receive an input gray-code word received by the input, the received register having an upper received-register that stores upper received bits and a lower received-register that stores N lower received bits of the input gray-code word;

a stored register that stores a corrected gray-code word, the stored register having an upper stored-register that stores upper stored bits and a lower stored-register that stores N lower stored bits of the corrected gray-code word;

an upper comparator, coupled to the received register and to the stored register, for comparing the upper received bits to the upper stored bits;

an upper loader, activated by the upper comparator when the upper received bits and the upper stored bits mis-match, for copying the upper received bits into the upper stored-register;

a low-bit generator that generates lower stored bits for loading into the lower stored-register such that the stored register has a lowest-possible value within the full sequence of gray-code values after loading; and

a full comparator, coupled to the received register and to the stored register, activated when the upper comparator determines that the upper received bits match the upper stored bits to compare the input gray-code word to the corrected gray-code word.



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U.S. References: Go to Result Set: All U.S. references   |  No patents reference this one   |   Backward references (16)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 9pp US3913094  1975-10 Wooton, III  The United States of America as represented by the Secretary of the Navy Count sequence test set for a disc type digital encoder
Buy PDF- 10pp US4975698  1990-12 Kagey  TRW Inc. Modified quasi-gray digital encoding technique
Buy PDF- 14pp US5097491  1992-03 Hall  National Semiconductor Corporation Modular gray code counter
Buy PDF- 15pp US5220586  1993-06 Tai  Texas Instruments Incorporated Circuitry and method for variable single transition counting
Buy PDF- 17pp US5394410  1995-02 Chen  International Business Machines Corporation Differentially coded and guard pulse position modulation for communication networks
Buy PDF- 10pp US5754614  1998-05 Wingen  VLSI Technology, Inc. Gray code counter
Buy PDF- 5pp US5923718  1999-07 Takahashi et al.  NEC Corporation Binary counter reading circuit
Buy PDF- 23pp US6304398  2001-10 Gaub et al.  Seagate Technology LLC Dual modulo gray code positioning system
Buy PDF- 13pp US6314154  2001-11 Pontius  VLSI Technology, INC Non-power-of-two Gray-code counter and binary incrementer therefor
Buy PDF- 8pp US6337893  2002-01 Pontius  Philips Electronics North America Corp. Non-power-of-two grey-code counter system having binary incrementer with counts distributed with bilateral symmetry
Buy PDF- 20pp US6400735  2002-06 Percey  Xilinx, Inc. Glitchless delay line using gray code multiplexer
Buy PDF- 13pp US6460160  2002-10 Classon  Motorola, Inc. Chase iteration processing for decoding input data
Buy PDF- 12pp US6553448  2003-04 Mannion  3Com Corporation Method for unit distance encoding of asynchronous pointers for non-power-of-two sized buffers
Buy PDF- 74pp US20010043150A1  2001-11 Tsukamoto   Analog to digital converter with encoder circuit and testing method therefor
Buy PDF- 75pp US20020044077A1  2002-04 Tsukamoto   Analog to digital converter with encoder circuit and testing method therefor
Buy PDF- 12pp US20040017303A1  2004-01 Loewen   Counter arrangement with recover function
       
Foreign References: None

Other References:
  • Mecklenburg, P., et al.; Correction of errors in multilevel Gray coded data; Information Theory, IEEE Transactions on;□□vol. 19, Issue 3, May 1973 pp. 336-340. (5 pages) Cited by 2 patents


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