a primary oscillator that generates a primary clock operating at a primary frequency;

a secondary oscillator that generates a secondary clock having a secondary frequency determined by a control voltage;

a phase detector that receives the primary clock or a derivative of the primary clock as a first input clock and the secondary clock or a derivative of the secondary clock as a second input clock, the phase detector comparing phases of the first input clock and the second input clock;

a holding circuit that determines the control voltage to the secondary oscillator, an input to the holding circuit being charged and discharged by the phase detector in response to phase comparison of the first and second input clocks;

a first delay circuit, receiving the primary clock and generating a delayed primary clock;

a second delay circuit, receiving the secondary clock and generating a delayed secondary clock;

a multiplexer, receiving the delayed primary clock from the first delay circuit, and receiving the delayed secondary clock from the second delay circuit, and receiving a select signal, for outputting the delayed primary clock as an output clock when the select signal is in a first state, and for outputting the delayed secondary clock as the output clock when the select signal is in a second state; and

a clock-failure detector, receiving the primary clock and receiving the secondary clock, for detecting a clock failure when the primary clock is not pulsing while the secondary clock is pulsing, the clock-failure detector generating the select signal in the second state when the clock failure is detected,

whereby the multiplexer selects the delayed secondary clock when the clock failure is detected.