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Title: US7174411: Dynamic allocation of PCI express lanes using a differential mux to an additional lane to a host
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Country: US United States of America

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18 pages

 
Inventor: Ngai, Henry P.; Coto De Caza, CA, United States of America

Assignee: Pericom Semiconductor Corp., San Jose, CA, United States of America
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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Published / Filed: 2007-02-06 / 2004-12-02

Application Number: US2004000904880

IPC Code: Advanced: G06F 1/00;
Core: more...

ECLA Code: G06F13/40D2;

U.S. Class: 710/316; 710/317; 710/305; 710/307;

Field of Search: 710/300-317,62-64,72,8-19,104-105

Priority Number:
2004-12-02  US2004000904880

Abstract:     Many Peripheral Component Interconnect Express (PCIE) lanes are available between a host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a transmit differential pair and a receive differential pair of data lines. The host has 2<SUP>N </SUP>primary lanes plus one extra lane. The extra lane is allocated to a slot when another slot uses all 2<SUP>N </SUP>primary lanes. The extra lane ensures that a low-priority peripheral has at least one lane when a high-priority peripheral requires all primary lanes. A partial cross-bar switching matrix between the host and peripheral slots switches lanes at the physical layer using transistor bus switches. A switch controller can be programmed by configuration software to enable transistor bus switches to allocate and connect host lanes to slot lanes. Peripherals can have 1, 2, 4, 8, 12, or 16 lanes allocated and may be inserted into any of the slots.

Attorney, Agent or Firm: gPatent LLC ; Auvinen, Stuart T. ;

Primary / Asst. Examiners: Rinehart, Mark H.; Phan, Raymond N

INPADOC Legal Status: Show legal status actions

Family: None

First Claim:
Show all 18 claims
    1. A re-configurable bus system comprising:

a host interface to a host;

a physical-layer switch;

primary lanes between the host interface and the physical-layer switch;

an extra lane between the host interface and the physical-layer switch;

wherein each of the primary lane and the extra lane is a bi-directional serial bus;

a first slot for receiving a first peripheral device;

a second slot for receiving a second peripheral device;

first lanes between the physical-layer switch and the first slot; and

second lanes between the physical-layer switch and the second slot;

wherein the physical-layer switch can be configured into a first maximum configuration wherein the primary lanes connect to the first lanes to the first slot, while the extra lane connects to the second slot;

wherein the physical-layer switch can be configured into a partitioned configuration wherein the primary lanes are partitioned among the first and second slot and the extra lane is not connected to either the first slot or to the second slot;

wherein the primary lanes comprise 2N lanes, wherein N is a whole number of 2 or more;

wherein the extra lane comprises exactly one lane;

whereby a total number of lanes from the host is exactly 2N+1 lanes.



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Forward References: Show 10 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (10)   |   Backward references (13)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 18pp US5191653  1993-03 Banks et al.  Apple Computer, Inc. IO adapter for system and IO buses having different protocols and speeds
Buy PDF- 8pp US6134621  2000-10 Kelley et al.  International Business Machines Corporation Variable slot configuration for multi-speed bus
Buy PDF- 32pp US6215412  2001-04 Franaszek et al.  International Business Machines Corporation All-node switch-an unclocked, unbuffered, asynchronous switching apparatus
Buy PDF- 40pp US6760327  2004-07 Manchester et al.  Cisco Technology, Inc. Rate adjustable backplane and method for a telecommunications node
Buy PDF- 5pp US6779734  2004-08 Hill  Nagracard S.A. Multiport card
Buy PDF- 10pp US6788682  2004-09 Kimmitt  3Com Corporation Mapping of packets between links of trunk groups using Mux/Demux devices
Buy PDF- 13pp US6792003  2004-09 Potluri et al.  Nortel Networks Limited Method and apparatus for transporting and aligning data across multiple serial data streams
Buy PDF- 81pp US20020105966A1  2002-08 Patel et al.   Backplane interface adapter with error control and redundant fabric
Buy PDF- 23pp US20030120852A1  2003-06 McConnell et al.   Multiple port allocation and configurations for different port operation modes on a host
Buy PDF- 21pp US20040088469A1  2004-05 Levy   Links having flexible lane allocation
Buy PDF- 36pp US20040179534A1  2004-09 Pettey et al.   Method and apparatus for shared I/O in a load/store fabric
Buy PDF- 21pp US20050088445A1  2005-04 Gonzalez et al.   Motherboard for supporting multiple graphics cards
Buy PDF- 7pp US20050102454A1  2005-05 McAfee et al.   Dynamic reconfiguration of PCI express links
       
Foreign References: None

Continuity Data:
Application Number Filed Notes

11161612   is a continuation in part of
>US2004000904880<  2004-12-02
     US7174411 issued 2007-02-06   Dynamic allocation of PCI express lanes using a differential mux to an additional lane to a host


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