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Title: |
US7191318:
Native copy instruction for file-access processor with copy-rule-based validation
[ Derwent Title ]

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Country: |
US United States of America

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Inventor: |
Tripathy, Tarun Kumar; Fremont, CA, United States of America
Mittal, Millind; Palo Alto, CA, United States of America
Popat, Kaushik L.; Pleasanton, CA, United States of America
Bodas, Amod; Cupertino, CA, United States of America

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Assignee: |
Alacritech, Inc., San Jose, CA, United States of America
other patents from ALACRITECH, INC. (782422) (approx. 20)
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Published / Filed: |
2007-03-13
/ 2003-04-07

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Application Number: |
US2003000249416

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IPC Code: |
Advanced:
G06F 9/00;
H04L 29/06;
Core:
more...

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ECLA Code: |
H04L29/06; H04L29/06F;

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U.S. Class: |
712/225;
710/022;
710/024;

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Field of Search: |
710/023

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Priority Number: |

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Abstract: |
A copy instruction executed by a functional-level instruction-set computing (FLIC) processor copies a variable-length data block from one resource to another resource through a cross-bar switch. Resources include general-purpose registers, input, output, and execution buffers, DRAM, SRAM, and other memory. A copy-with-validate instruction has an operand pointing to a first rule in an immediate rule table. The first rule controls validation of a first data-item in the data being copied. Validation includes range and equality checking of the data-item. The value of the data-item or the current offset can be written to a register. A format field in the rule indicates the size of the data-item, or the size is read from the data-item for variable-size formats. The current offset is incremented by the size. The next data-item is validated by a next rule, and other rules in the immediate table control validation of other data-items in the data block.

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Attorney, Agent or Firm: |
Lauer, Mark ;
Silicon Edge Law Group LLP ;
Auvinen, Stuart ;

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Primary / Asst. Examiners: |
Chan, Eddie; Petranek, Jacob

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INPADOC Legal Status: |
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Parent Case: |
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation-in-part of the co-pending application for Functional-Level Instruction-Set Computer Architecture for Processing Application-Layer Content-Service Requests Such as File-Access Requests, U.S. Ser. No. 10/248,029, filed Dec. 12, 2002.

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Family: |
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First Claim:
Show all 21 claims |
1. A processor comprising: an instruction decoder for decoding instructions in a program being executed by the processor, the instructions including a copy instruction; a plurality of memory resources for storing data, including a register file containing registers that store operands operated upon by the instructions, the registers being identified by operand fields in the instructions decoded by the instruction decoder; a copy unit, activated by the instruction decoder when the copy instruction is decoded, for performing a copy operation indicated by the copy instruction, the copy operation reading a data block from a source resource in the plurality of memory resources, the source resource specified by the copy instruction, the copy operation writing the data block to a destination resource in the plurality of memory resources, the destination resource specified by the copy instruction, the copy operation parsing the data block to create a series of pointers that correspond to a series of data-items within the data block, wherein at least one of the data-items includes a file name or file handle.

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Background / Summary: |
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Drawing Descriptions: |
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Description: |
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Forward References: |
Show 13 U.S. patent(s) that reference this one

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Backward references (21)
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