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Title: US7191318: Native copy instruction for file-access processor with copy-rule-based validation
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Country: US United States of America

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23 pages

 
Inventor: Tripathy, Tarun Kumar; Fremont, CA, United States of America
Mittal, Millind; Palo Alto, CA, United States of America
Popat, Kaushik L.; Pleasanton, CA, United States of America
Bodas, Amod; Cupertino, CA, United States of America

Assignee: Alacritech, Inc., San Jose, CA, United States of America
other patents from ALACRITECH, INC. (782422) (approx. 20)
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Published / Filed: 2007-03-13 / 2003-04-07

Application Number: US2003000249416

IPC Code: Advanced: G06F 9/00; H04L 29/06;
Core: more...

ECLA Code: H04L29/06; H04L29/06F;

U.S. Class: 712/225; 710/022; 710/024;

Field of Search: 710/023

Priority Number:
2003-04-07  US2003000249416
2002-12-12  US2002000248029

Abstract:     A copy instruction executed by a functional-level instruction-set computing (FLIC) processor copies a variable-length data block from one resource to another resource through a cross-bar switch. Resources include general-purpose registers, input, output, and execution buffers, DRAM, SRAM, and other memory. A copy-with-validate instruction has an operand pointing to a first rule in an immediate rule table. The first rule controls validation of a first data-item in the data being copied. Validation includes range and equality checking of the data-item. The value of the data-item or the current offset can be written to a register. A format field in the rule indicates the size of the data-item, or the size is read from the data-item for variable-size formats. The current offset is incremented by the size. The next data-item is validated by a next rule, and other rules in the immediate table control validation of other data-items in the data block.

Attorney, Agent or Firm: Lauer, Mark ; Silicon Edge Law Group LLP ; Auvinen, Stuart ;

Primary / Asst. Examiners: Chan, Eddie; Petranek, Jacob

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Related Applications:
Application Number Filed Patent Pub. Date  Title
US2002000248029 2002-12-12       


       
Parent Case: CROSS REFERENCE TO RELATED APPLICATIONS
    This application is a continuation-in-part of the co-pending application for Functional-Level Instruction-Set Computer Architecture for Processing Application-Layer Content-Service Requests Such as File-Access Requests, U.S. Ser. No. 10/248,029, filed Dec. 12, 2002.

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First Claim:
Show all 21 claims
    1. A processor comprising:

an instruction decoder for decoding instructions in a program being executed by the processor, the instructions including a copy instruction;

a plurality of memory resources for storing data, including a register file containing registers that store operands operated upon by the instructions, the registers being identified by operand fields in the instructions decoded by the instruction decoder;

a copy unit, activated by the instruction decoder when the copy instruction is decoded, for performing a copy operation indicated by the copy instruction, the copy operation reading a data block from a source resource in the plurality of memory resources, the source resource specified by the copy instruction, the copy operation writing the data block to a destination resource in the plurality of memory resources, the destination resource specified by the copy instruction, the copy operation parsing the data block to create a series of pointers that correspond to a series of data-items within the data block, wherein at least one of the data-items includes a file name or file handle.



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Forward References: Show 13 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (13)   |   Backward references (21)   |   Citation Link

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Foreign References: None

Other References:
  • Weaver et al. “The SPARC Architecture Manual” Version 9, pp. 194-197, 2000.


  • Continuity Data:
    Application Number Filed Notes

    US2003000249416 2003-04-07  is a related to the prior publication
         US20040117602A1 issued 2004-06-17  Native Copy Instruction for File-Access Processor with Copy-Rule-Based Validation

    >US2003000249416< 2003-04-07  is a continuation in part of
    US2002000248029  2002-12-12   (pending) [presumed granted]
         US7254696 issued 2007-08-07   Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests

    US2002000249416   is a continuation in part of
    US2002000248029  2002-12-12   (pending) [presumed granted]
         US7254696 issued 2007-08-07   Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests


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