a data error-correction code (ECC) generator, receiving write data, for generating data ECC bits containing correction code capable of correcting an error in B data bits, and also capable of detecting an error in 2*B data bits;

an address linear block code generator, receiving a write address corresponding to the write data, for generating address check bits from the write address using a linear block code function;

wherein the address check bits comprise B bits, and the write address comprises at least 4×B bits, wherein the linear block code function compresses the write address;

a first merge unit, receiving a first B-bit portion of the data ECC bits and receiving the address check bits, for merging the first B-bit portion of the data ECC bits with the address check bits to generate a first merged B-bit portion of a merged ECC codeword;

a second merge unit, receiving a second B-bit portion of the data ECC bits and receiving the address check bits, for merging the second B-bit portion of the data ECC bits with the address check bits to generate a second merged B-bit portion of the merged ECC codeword;

wherein the merged ECC codeword has a third portion that contains data ECC bits from the data ECC generator that are not input to the first or second merge units;

a write interface to a memory for writing the merged ECC codeword to the memory that stores the write data at a location determined by the write address;

a read interface to the memory for reading a stored ECC codeword and read data from a location determined by a read address;

a second ECC generator, receiving the read data from the memory, for generating read ECC bits;

a second address linear block code generator, receiving the read address corresponding to the read data, for generating read address check bits from the read address using the linear block code function;

a first de-merge unit, receiving a first B-bit portion of the stored ECC codeword and receiving the read address check bits, for de-merging the first B-bit portion of the stored ECC codeword from the read address check bits to generate a first de-merged B-bit portion of a de-merged ECC codeword;

a second de-merge unit, receiving a second B-bit portion of the stored ECC codeword and receiving the read address check bits, for de-merging the second B-bit portion of the stored ECC codeword from the read address check bits to generate a second de-merged B-bit portion of a de-merged ECC codeword;

a comparator, receiving the read ECC bits from the second ECC generator and receiving the de-merged ECC codeword, for signaling an address error when first B-bit portions and second B-bit portions of the read ECC bits and the de-merged ECC codeword mis-match; and

a data corrector, coupled to the comparator, for correcting up to B bits of the read data to generate corrected data using the de-merged ECC codeword to locate errors in the read data when the address error is not signaled by the comparator determines that the read ECC bits do not match the de-merged ECC codeword,

whereby data is corrected and address errors are signaled using merged ECC codewords stored in the memory.