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 Title: |
US7216214:
System and method for re-ordering memory references for access to memory
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Dally, William J.; Stanford, CA, United States of America
Rixner, Scott W.; Mountain View, CA, United States of America
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| Assignee: |
The Massachusetts Institute of Technology, Cambridge, MA, United States of America
The Board of Trustees of the Leland Stanford Junior University, Pala Alto, CA, United States of America
other patents from MASSACHUSETTS INSTITUTE OF TECHNOLOGY (357270) (approx. 2,706)
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| Published / Filed: |
2007-05-08
/ 2006-05-15
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| Application Number: |
US2006000434392
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| IPC Code: |
Advanced:
G06F 12/00;
Core:
more...
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| ECLA Code: |
G11C8/04;
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| U.S. Class: |
711/217;
711/105;
711/158;
365/230.01;
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| Field of Search: |
365/230.03,230.01,189.05
711/217,105,158
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| Government Interest: |
FEDERALLY-SPONSORED RESEARCH AND DEVELOPMENT
This invention was made with Government Support under contract DABT63-96-C-0037 awarded by the Department of the Army. The U.S. Government has certain rights in this invention.
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| Priority Number: |
| 2006-05-15 |
US2006000434392 |
| 2004-12-21 |
US2004000019979 |
| 1999-09-13 |
US1999000394222 |
| 1998-09-14 |
US1998000100147P |
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| Abstract: |
A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).
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| Attorney, Agent or Firm: |
Crawford Maunu PLLC ;
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| Primary / Asst. Examiners: |
Lane, Jack A.;
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| INPADOC Legal Status: |
None
Family Legal Status Report
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| Parent Case: |
RELATED PATENT DOCUMENTS
This application is a continuation of U.S. patent application Ser. No. 11/019,979 filed on Dec. 21, 2004, to issue as U.S. Pat. No. 7,047,391 on May 16, 2006 to which priority is claimed under 35 U.S.C. § 120. U.S. patent application Ser. No. 11/019,979 is further a continuation of U.S. patent application Ser. No. 09/394,222 filed on Sep. 13, 1999 (now abandoned), which claimed benefit under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No. 60/100,147 filed on Sep. 14, 1998.
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| Family: |
Show 4 known family members
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First Claim:
Show all 22 claims |
1. A computer arrangement that receives addresses corresponding to data in an order, the computer arrangement comprising: an address buffer that receives addresses in said order; a control circuit that selects, as a function of an active location in a memory and independent of any data previously provided with the addresses by the computer arrangement to convey the addresses priority and purpose, a memory reference corresponding to at least one of the received addresses, the memory reference being selected to access the memory in an order different than the order in which the addresses were received by the address buffer; and a read buffer that receives data read out from the memory.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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