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Title: US7221727: All-digital phase modulator/demodulator using multi-phase clocks and digital PLL
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Country: US United States of America

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14 pages

 
Inventor: Co, Ramon S.; Trabuco Canyon, CA, United States of America

Assignee: Kingston Technology Corp., Fountain Valley, CA, United States of America
other patents from KINGSTON TECHNOLOGY COMPANY (741845) (approx. 14)
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Published / Filed: 2007-05-22 / 2003-04-01

Application Number: US2003000249335

IPC Code: Advanced: H03C 3/09; H03D 3/24; H03L 7/081; H04L 27/22;
Core: H03C 3/00; H03D 3/00; more...

ECLA Code: H03C3/09A; H03L7/081A1; H04L27/22;

U.S. Class: 375/376; 327/147;

Field of Search: 375/371,373,375,376,316,324,327,354,374 327/141,144,147,155,156

Priority Number:
2003-04-01  US2003000249335

Abstract:     Multi-phase clocks are used to encode and decode signals that are phase-modulated. The input signal is phase-compared with a feedback clock. Phase differences increment or decrement an up/down counter. The count value from the up/down counter is applied to a phase rotator, which selects one clock phase from a bank of multi-phase clocks. The multi-phase clocks have the same frequency, but are offset in phase from each other. An output divider divides the selected multi-phase clock to generate a phase-modulated output. A feedback divider divides a fixed-phase clock from the multi-phase clocks to generate the feedback clock. An analog or a digital front-end may be used to convert analog inputs to digital signals to increment or decrement the counter, or to encode multiple digital bits as phase assignments. For a de-modulator, a digital-to-analog converter (DAC) or a digital decoder produces the final output from the count of the up/down counter.

Attorney, Agent or Firm: g Patent LLC ; Auvinen, Stuart T. ;

Primary / Asst. Examiners: Burd, Kevin;

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First Claim:
Show all 9 claims
    1. A modulator comprising:

a plurality of multi-phase clocks, each clock of multi-phase clocks having a same frequency but being offset in phase from other clocks in the plurality of multi-phase clocks;

a phase rotator, coupled to the plurality of multi-phase clocks, for selecting a selected clock from the plurality of multi-phase clocks in response to a count value;

an up/down counter, responsive to an increment signal, for increasing or decreasing the count value to the phase rotator;

an output divider, receiving the selected clock from the phase rotator, for generating a phase-modulated output signal that is phase-modulated in response to changes in the count value from the up/down counter;

a feedback divider, receiving a fixed-phase clock having the same frequency as the plurality of multi-phase clocks, for generating a feedback clock;

wherein the up/down counter receives the feedback clock, the up/down counter changing the count value synchronously to the feedback clock;

wherein the fixed-phase clock is one of the plurality of multi-phase clocks permanently selected by the phase rotator for output to the feedback divider; and

a clocked front-end, receiving the feedback clock and an input signal, for generating the increment signal in response to changes of the input signal, wherein the feedback clock synchronizes the clocked front-end,

whereby changes to the input signal cause the phase rotator to select different phase clocks from the plurality of multi-phase clocks to adjust phase of the phase-modulated output signal.



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Forward References: Show 3 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (3)   |   Backward references (22)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 10pp US3916340  1975-10 Shuda  Wisconsin Alumni Research Foundation Multimode oscillators
Buy PDF- 19pp US4513427  1985-04 Borriello et al.  Xerox Corporation Data and clock recovery system for data communication controller
Buy PDF- 11pp US4584695  1986-04 Wong et al.  National Semiconductor Corporation Digital PLL decoder
Buy PDF- 11pp US4821297  1989-04 Bergmann et al.  American Telephone and Telegraph Company, AT&T Bell Laboratories Digital phase locked loop clock recovery scheme
Buy PDF- 20pp US5491729  1996-02 Co et al.  3Com Corporation Digital phase-locked data recovery circuit
Buy PDF- 12pp US5502750  1996-03 Co et al.  Pericom Semiconductor Corp. Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer for a token ring network
Buy PDF- 12pp US5602882  1997-02 Co et al.  Pericom Semiconductor Corp. Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer
Buy PDF- 17pp US6028727  2000-02 Vishakhadatta et al.  Cirrus Logic, Inc. Method and system to improve single synthesizer setting times for small frequency steps in read channel circuits
Buy PDF- 9pp US6087968  2000-07 Roza  U.S. Philips Corporation Analog to digital converter comprising an asynchronous sigma delta modulator and decimating digital filter
Buy PDF- 35pp US6175385  2001-01 Kohiyama et al.  Fujitsu Limited Digital PLL circuit for MPED stream and MPEG decoder having the digital PLL circuit
Buy PDF- 13pp US6219397  2001-04 Park  Samsung Electronics Co., Ltd. Low phase noise CMOS fractional-N frequency synthesizer for wireless communications
Buy PDF- 29pp US6259482  2001-07 Easley et al.   Digital BTSC compander system
Buy PDF- 31pp US6359949  2002-03 Okada et al.  Mitsumi Electric Co., Ltd. Demodulation circuit, a decode circuit and a digital PLL circuit for an optical disc apparatus
Buy PDF- 10pp US6392496  2002-05 Lee et al.  LG Information & Communications, Ltd. Digital PLL circuit having a look-up table and method thereof
Buy PDF- 10pp US6449017  2002-09 Chen   RGB self-alignment and intelligent clock recovery
Buy PDF- 8pp US6493408  2002-12 Kobayashi  NEC Corporation Low-jitter data transmission apparatus
Buy PDF- 9pp US6693987  2004-02 Hattori  Pericom Semiconductor Corp. Digital-to-analog DAC-driven phase-locked loop PLL with slave PLL's driving DAC reference voltages
Buy PDF- 30pp US20020033737A1  2002-03 Staszewski et al.   SYSTEM AND METHOD FOR TIME DITHERING A DIGITALLY-CONTROLLED OSCILLATOR TUNING INPUT
Buy PDF- 20pp US20020163325A1  2002-11 Nilsson   Linear fast-locking digital phase detector
Buy PDF- 15pp US20020191727A1  2002-12 Staszewski et al.   Digital phase locked loop
Buy PDF- 12pp US20030039330A1  2003-02 Castiglione et al.   PROCESS FOR GENERATING A VARIABLE FREQUENCY SIGNAL, FOR INSTANCE FOR SPREADING THE SPECTRUM OF A CLOCK SIGNAL, AND DEVICE THEREFOR
Buy PDF- 15pp US20030040276A1  2003-02 Corn   Method and apparatus to record and replay radio programs
       
Foreign References: None

Other References:
  • M. Schwartz, “Information Transmission, Modulation, and Noise”, 3rd edition, McGraw-Hill, 1980, pp. 224-233.


  • Continuity Data:
    Application Number Filed Notes

    US2003000249335 2003-04-01  is a related to the prior publication
         US20040196939A1 issued 2004-10-07  All-Digital Phase Modulator/Demodulator Using Multi-Phase Clocks and Digital PLL

    US2007000692472 2007-03-28  is a continuation in part of
    >US2003000249335<  2003-04-01   (granted)
         US7221727 issued 2007-05-22   All-digital phase modulator/demodulator using multi-phase clocks and digital PLL


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