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Title: US7259589: Visual or multimedia interface bus switch with level-shifted ground and input protection against non-compliant transmission-minimized differential signaling (TMDS) transmitter
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Country: US United States of America

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14 pages

 
Inventor: Hui, Chi-Hung; Saratoga, CA, United States of America
Li, Xianxin; Milpitas, CA, United States of America

Assignee: Pericom Semiconductor Corp., San Jose, CA, United States of America
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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Published / Filed: 2007-08-21 / 2005-09-16

Application Number: US2005000162638

IPC Code: Advanced: H03K 19/0175; H03K 19/096;
Core: more...

ECLA Code: H03K19/0185; H03K19/096;

U.S. Class: 326/063; 326/062; 326/065; 326/081; 326/095; 326/098; 327/333;

Field of Search: 326/062,63,81,95,98 327/333

Priority Number:
2005-09-16  US2005000162638

Abstract:     A bus switch chip is limited to operating with a power-supply voltage of 1.8 volts relative to a 0-volt ground. Differential bus signals switched through the bus switch chip swing from 2.7 to 3.3 volts, well above the chip's specified power-supply voltage. The bus switch chip is level-shifted by applying a 1.5-volt signal as the chip's ground, and a 3.3-volt signal as its power supply, so the chip's net power supply is within the specification at 1.8 volts. High-Definition Multimedia Interface (HDMI) and Digital Visual Interface (DVI) require that the differential signals are never driven to ground. However, some non-compliant video transmitters drive differential signals to ground when disabled. External pullup resistors or internal pullup transistors in the bus switch chip are added to the bus signals from non-compliant transmitters to pull disabled signals above the 1.5-volt chip ground to prevent damage from signals below the chip's 1.5-volt ground.

Attorney, Agent or Firm: gPatent LLC ; Auvinen, Stuart T. ;

Primary / Asst. Examiners: Barnie, Rexford; White, Dylan

Family: None

First Claim:
Show all 21 claims
    1. A differential signaling system comprising:

a bus switch chip having a plurality of channels that connect a first bus to a second bus in response to a control signal being in a connect state, and that isolate the first bus from the second bus in response to the control signal being in an isolate state, the bus switch chip having a power-supply pin and a ground pin;

a first differential transmitter that generates differential signals applied to the bus switch chip as the first bus;

a differential receiver, coupled to the second bus from the bus switch chip, the differential receiver receiving differential signals passed through the bus switch chip from the first differential transmitter when the control signal is in the connect state;

a ground supply having a ground voltage;

a power supply having a power supply voltage above the ground voltage;

a mid-level supply, having a mid voltage between the power supply voltage and the ground voltage;

wherein the power supply voltage from the power supply is applied to the power-supply pin of the bus switch chip;

wherein the mid voltage from the mid-level supply is applied to the ground pin of the bus switch chip;

wherein the differential signals generated by the first differential transmitter swing within a voltage range that is between the mid voltage and the power supply voltage; and

a plurality of pull-ups, coupled between the power supply voltage and the first bus, for driving the differential signals from the first differential transmitter above the mid voltage when the first differential transmitter is disabled,

whereby the bus switch chip is supply-level shifted to pass the differential signals at the voltage range above the mid voltage applied to the ground pin of the bus switch chip.



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Forward References: Show 1 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (1)   |   Backward references (17)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 12pp US4920284  1990-04 Denda  NEC Corporation CMOS level converter circuit with reduced power consumption
Buy PDF- 13pp US5321324  1994-06 Hardee et al.  United Memories, Inc. Low-to-high voltage translator with latch-up immunity
Buy PDF- 15pp US5583454  1996-12 Hawkins et al.  Advanced Micro Devices, Inc. Programmable input/output driver circuit capable of operating at a variety of voltage levels and having a programmable pullup/pulldown function
Buy PDF- 14pp US5666071  1997-09 Hawkins et al.  Advanced Micro Devices, Inc. Device and method for programming high impedance states upon select input/output pads
Buy PDF- 12pp US5896044  1999-04 Walden  Lucent Technologies, Inc. Universal logic level shifting circuit and method
Buy PDF- 8pp US5933025  1999-08 Nance et al.  Xilinx, Inc. Low voltage interface circuit with a high voltage tolerance
Buy PDF- 20pp US6043699  2000-03 Shimizu  Sony Corporation Level shift circuit
Buy PDF- 8pp US6683473  2004-01 Fotouhi  Exar Corporation Input termination with high impedance at power off
Buy PDF- 16pp US6724224  2004-04 Li  Pericom Semiconductor Corp. Bus relay and voltage shifter without direction control input
Buy PDF- 15pp US6724592  2004-04 Tong et al.  Pericom Semiconductor Corp. Substrate-triggering of ESD-protection device
Buy PDF- 8pp US6747503  2004-06 Fotouhi  Exar Corporation CMOS transmission gate with high impedance at power off
Buy PDF- 14pp US6750686  2004-06 Wang  Koninklijke Philips Electronics N.V. Frequency divider with reduced power consumption, apparatus based thereon, and method for power efficient frequency divider
Buy PDF- 10pp US6965253  2005-11 Chen et al.  Pericom Semiconductor Corp. Reduced-capacitance bus switch in isolated P-well shorted to source and drain during switching
Buy PDF- 16pp US20010007430A1  2001-07 Goodell   HIGH FREQUENCY MOSFET SWITCH
Buy PDF- 18pp US20020175700A1  2002-11 Nagano et al.   Impedance adjustment circuit
Buy PDF- 11pp US20040158873A1  2004-08 Pasqualino   Method and system for generating high definition multimedia interface (HDMI) codewords using a TMDS encoder/decoder
Buy PDF- 56pp US20050179465A1  2005-08 Otsuka et al.   High-speed signal transmission system
       
Foreign References: None

Other References:
  • Digital Display Working Group, “Digital Visual Interface DVI”, Spec. rev. 1.0, Apr. 2, 1999, pp. 1-6, 33-39.
  • Hitachi et al., “High-Definition Multimedia Interface Specification Version 1.1”, May 20, 2004, pp. 1-9, 31-42.


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